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  /external/llvm/lib/Target/R600/
SILowerControlFlow.cpp 19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
179 unsigned Vcc = MI.getOperand(1).getReg();
182 .addReg(Vcc);
231 unsigned Vcc = MI.getOperand(1).getReg();
235 .addReg(Vcc)
    [all...]
AMDGPUAsmPrinter.cpp 167 if (reg == AMDGPU::VCC) {
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
AMDGPUAsmPrinter.cpp 80 if (reg == AMDGPU::VCC) {
SIGenRegisterInfo.pl 90 def VCC : SIReg<"VCC">;
172 def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
273 #Add VCC to SReg_64
275 push (@registers, 'VCC')
SIISelLowering.cpp 208 AMDGPU::VCC)
239 AMDGPU::VCC)
245 .addReg(AMDGPU::VCC)
286 /// VCC register. In the VALU context, VCC is a one bit register, but in the
287 /// SALU context the VCC is a 64-bit register (1-bit per thread). Since only
288 /// the SALU can perform operations on the VCC register, we need to promote
  /external/mesa3d/src/gallium/drivers/radeon/
AMDGPUAsmPrinter.cpp 80 if (reg == AMDGPU::VCC) {
SIGenRegisterInfo.pl 90 def VCC : SIReg<"VCC">;
172 def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
273 #Add VCC to SReg_64
275 push (@registers, 'VCC')
SIISelLowering.cpp 208 AMDGPU::VCC)
239 AMDGPU::VCC)
245 .addReg(AMDGPU::VCC)
286 /// VCC register. In the VALU context, VCC is a one bit register, but in the
287 /// SALU context the VCC is a 64-bit register (1-bit per thread). Since only
288 /// the SALU can perform operations on the VCC register, we need to promote
  /external/clang/unittests/AST/
CommentParser.cpp     [all...]

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