| /external/valgrind/main/VEX/priv/ |
| host_x86_isel.c | 209 static void addInstr ( ISelEnv* env, X86Instr* instr )
311 addInstr(env,
318 addInstr(env,
349 addInstr(env, X86Instr_Push(iselIntExpr_RMI(env, arg)));
355 addInstr(env, X86Instr_Push(X86RMI_Reg(rHi)));
356 addInstr(env, X86Instr_Push(X86RMI_Reg(rLo)));
376 addInstr(env, X86Instr_Call( cc, toUInt(Ptr_to_ULong(cee->addr)),
528 addInstr( env, mk_iMOVsd_RR( tmpregs[argregX], argregs[argregX] ) );
538 addInstr(env, X86Instr_Alu32R(Xalu_MOV,
549 addInstr(env, mk_iMOVsd_RR( hregX86_EBP(), argregs[0]))
[all...] |
| host_amd64_isel.c | 176 static void addInstr ( ISelEnv* env, AMD64Instr* instr )
323 addInstr(env,
331 addInstr(env,
343 addInstr( env, AMD64Instr_Push(AMD64RMI_Imm( (UInt)uimm64 )) );
346 addInstr( env, AMD64Instr_Imm64(uimm64, tmp) );
347 addInstr( env, AMD64Instr_Push(AMD64RMI_Reg(tmp)) );
505 addInstr (that is, commit to) any instructions until we're
530 addInstr(env, fastinstrs[i]);
551 addInstr(env, mk_iMOVsd_RR( hregAMD64_RBP(), tmpregs[argreg]));
581 addInstr( env, mk_iMOVsd_RR( tmpregs[i], argregs[i] ) )
[all...] |
| host_s390_isel.c | 170 addInstr(ISelEnv *env, s390_insn *insn)
492 addInstr(env, s390_insn_move(sizeof(ULong), tmpregs[argreg],
522 addInstr(env, s390_insn_move(size, finalreg, tmpregs[i]));
528 addInstr(env, s390_insn_helper_call(cc, (Addr64)target, n_args,
575 addInstr(env, s390_insn_move(4, cc0, cc_s390));
576 addInstr(env, s390_insn_alu(4, S390_ALU_AND, cc0, s390_opnd_imm(1)));
579 addInstr(env, s390_insn_move(4, cc1, cc_s390));
580 addInstr(env, s390_insn_alu(4, S390_ALU_RSH, cc1, s390_opnd_imm(1)));
583 addInstr(env, s390_insn_move(4, b2, cc0));
584 addInstr(env, s390_insn_alu(4, S390_ALU_AND, b2, s390_opnd_reg(cc1)))
[all...] |
| host_mips_isel.c | 156 static void addInstr(ISelEnv * env, MIPSInstr * instr)
192 addInstr(env, MIPSInstr_Alu(Malu_ADD, sp, sp, MIPSRH_Imm(True,
200 addInstr(env, MIPSInstr_Alu(Malu_SUB, sp, sp,
272 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, irrm,
274 addInstr(env, MIPSInstr_Alu(Malu_XOR, tmp, irrm, MIPSRH_Reg(tmp)));
275 addInstr(env, MIPSInstr_Alu(Malu_AND, irrm, tmp, MIPSRH_Imm(False, 3)));
277 addInstr(env, MIPSInstr_MfFCSR(fcsr_old));
282 addInstr(env, MIPSInstr_Store(4, am_addr, fcsr_old, mode64));
285 addInstr(env, MIPSInstr_MtFCSR(irrm));
295 addInstr(env, MIPSInstr_Load(4, fcsr, am_addr, mode64))
[all...] |
| host_ppc_isel.c | 327 static void addInstr ( ISelEnv* env, PPCInstr* instr )
486 addInstr(env, PPCInstr_Alu( Palu_ADD, sp, sp,
494 addInstr(env, PPCInstr_Alu( Palu_SUB, sp, sp,
508 addInstr(env, mk_iMOVds_RR(r, StackFramePtr(env->mode64)));
510 addInstr(env, PPCInstr_Alu( Palu_ADD, r, r,
513 addInstr(env,
515 addInstr(env, PPCInstr_Alu(Palu_AND, r,r, PPCRH_Reg(align16)));
537 addInstr(env, PPCInstr_Store( 4, am_addr0, r_srcHi, env->mode64 ));
538 addInstr(env, PPCInstr_Store( 4, am_addr1, r_srcLo, env->mode64 ));
541 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_dst, am_addr0))
[all...] |
| host_arm_isel.c | 145 static void addInstr ( ISelEnv* env, ARMInstr* instr )
304 addInstr(env, ARMInstr_Imm32(rTmp, DEFAULT_FPSCR));
305 addInstr(env, ARMInstr_FPSCR(True/*toFPSCR*/, rTmp));
342 addInstr(env, ARMInstr_Shift(ARMsh_SHL, tL, irrm, ARMRI5_I5(1)));
343 addInstr(env, ARMInstr_Shift(ARMsh_SHR, tR, irrm, ARMRI5_I5(1)));
344 addInstr(env, ARMInstr_Alu(ARMalu_AND, tL, tL, ARMRI84_I84(2,0)));
345 addInstr(env, ARMInstr_Alu(ARMalu_AND, tR, tR, ARMRI84_I84(1,0)));
346 addInstr(env, ARMInstr_Alu(ARMalu_OR, t3, tL, ARMRI84_R(tR)));
347 addInstr(env, ARMInstr_Shift(ARMsh_SHL, t3, t3, ARMRI5_I5(22)));
348 addInstr(env, ARMInstr_FPSCR(True/*toFPSCR*/, t3))
[all...] |
