| /external/qemu/ |
| gen-icount.h | 17 tcg_gen_ld_i32(count, cpu_env, offsetof(CPUState, icount_decr.u32));
23 tcg_gen_st16_i32(count, cpu_env, offsetof(CPUState, icount_decr.u16.low));
39 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io));
46 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io));
|
| /external/qemu/target-i386/ |
| translate.c | 64 static TCGv_ptr cpu_env; variable
279 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
281 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
285 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
289 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
292 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
296 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
301 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
321 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
325 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET)
[all...] |
| /external/qemu/hw/ |
| apic.c | 67 CPUState *cpu_env; member in struct:APICState
242 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
247 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
253 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
368 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
490 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
645 apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
906 int bsp = cpu_is_bsp(s->cpu_env);
911 cpu_reset(s->cpu_env);
912 apic_init_reset(s->cpu_env);
[all...] |
| /external/qemu/target-arm/ |
| translate.c | 90 static TCGv_ptr cpu_env; variable
117 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
144 tcg_gen_ld_i32(tmp, cpu_env, offset);
152 tcg_gen_st_i32(var, cpu_env, offset);
378 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
392 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
393 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
533 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
580 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE))
[all...] |
| /external/qemu/target-mips/ |
| translate.c | 429 static TCGv_ptr cpu_env; variable
557 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
562 tcg_gen_add_ptr(addr, cpu_env, addr);
580 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
585 tcg_gen_add_ptr(addr, cpu_env, addr);
597 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
602 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
607 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
612 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
618 tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d))
[all...] |
