| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 30 static bool isReg(const MCInst &MI, unsigned OpNo) {
31 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
164 if (Op.isReg()) {
234 return isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
237 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
240 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
243 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
246 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);
249 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
252 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 188 return isReg() ? 0 : SubReg_TargetFlags;
191 assert(!isReg() && "Register operands can't have target flags");
196 assert(!isReg() && "Register operands can't have target flags");
223 /// isReg - Tests if this is a MO_Register operand.
224 bool isReg() const { return OpKind == MO_Register; }
260 assert(isReg() && "This is not a register operand!");
265 assert(isReg() && "Wrong MachineOperand accessor");
270 assert(isReg() && "Wrong MachineOperand accessor");
275 assert(isReg() && "Wrong MachineOperand accessor");
280 assert(isReg() && "Wrong MachineOperand accessor")
[all...] |
| LiveVariables.h | 215 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
251 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 18 if (Op.isReg()) {
|
| /external/llvm/lib/CodeGen/ |
| AntiDepBreaker.h | 64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
|
| DeadMachineInstructionElim.cpp | 68 if (MO.isReg() && MO.isDef()) {
125 if (!MO.isReg() || !MO.isDef())
154 if (MO.isReg() && MO.isDef()) {
173 if (MO.isReg() && MO.isUse()) {
|
| MachineInstr.cpp | 92 assert(isReg() && "Wrong MachineOperand accessor");
113 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
116 if (isReg() && isOnRegUseList())
139 bool WasReg = isReg();
580 if (Operands[i].isReg())
589 if (Operands[i].isReg())
642 bool isImpReg = Op.isReg() && Op.isImplicit();
644 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
686 if (NewMO->isReg()) {
721 if (Operands[i].isReg())
[all...] |
| ProcessImplicitDefs.cpp | 71 if (MO->isReg() && MO->isUse() && MO->readsReg())
106 if (!MO->isReg())
|
| TargetInstrInfo.cpp | 122 if (HasDef && !MI->getOperand(0).isReg())
133 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
192 if (!MI->getOperand(SrcOpIdx1).isReg() ||
193 !MI->getOperand(SrcOpIdx2).isReg())
227 if (MO.isReg()) {
442 if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
480 if (!MO.isReg()) continue;
|
| MachineInstrBundle.cpp | 54 if (MO.isReg() && MO.isInternalRead())
126 if (!MO.isReg())
257 if (!MO.isReg() || MO.getReg() != Reg)
294 if (!MO.isReg())
|
| /external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 18 if (Op.isReg()) {
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 113 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
124 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
136 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
148 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
159 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
171 assert(MI.getOperand(OpNo+1).isReg());
189 assert(MI.getOperand(OpNo+1).isReg());
206 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups);
241 if (MO.isReg()) {
|
| /external/llvm/include/llvm/MC/MCParser/ |
| MCParsedAsmOperand.h | 47 /// isReg - Is this a register operand?
48 virtual bool isReg() const = 0;
|
| /external/llvm/include/llvm/MC/ |
| MachineLocation.h | 49 bool isReg() const { return IsRegister; }
|
| MCInst.h | 56 bool isReg() const { return Kind == kRegister; }
64 assert(isReg() && "This is not a register operand!");
70 assert(isReg() && "This is not a register operand!");
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 252 bool isReg() const { return Kind == CV_Register; }
256 assert(isReg() && "Wrong CountValue accessor");
260 assert(isReg() && "Wrong CountValue accessor");
270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
527 if (Op1.isReg()) {
564 if (InitialValue->isReg()) {
591 if (InitialValue->isReg()) {
598 if (EndValue->isReg()) {
624 if (Start->isReg()) {
629 if (End->isReg()) {
[all...] |
| HexagonNewValueJump.cpp | 150 if (II->getOperand(i).isReg() &&
474 MI->getOperand(0).isReg() &&
482 isSecondOpReg = MI->getOperand(2).isReg();
516 if (MI->getOperand(0).isReg() &&
573 if (MO.isReg() && MO.isUse()) {
580 if (localMO.isReg() && localMO.isUse() &&
635 if (cmpInstr->getOperand(0).isReg() &&
638 if (cmpInstr->getOperand(1).isReg() &&
|
| HexagonVLIWPacketizer.cpp | 356 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
483 if (MI->getOperand(opNum).isReg() &&
489 if (MI->getOperand(opNum).isReg() &&
498 assert(MI->getOperand(1).isReg() &&
504 assert(MI->getOperand(0).isReg() &&
547 if (GetStoreValueOperand(MI).isReg() &&
611 if ( PacketMI->getOperand(opNum).isReg())
623 if ( MI->getOperand(opNum).isReg())
677 if (MI->getOperand(opNum).isReg() &&
691 GetStoreValueOperand(MI).isReg() &
[all...] |
| HexagonCopyToCombine.cpp | 120 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isReg());
131 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
142 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isGlobal());
214 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
371 if (!Op.isReg() || !Op.isUse() || !Op.getReg())
401 if (!Op.isReg() || !Op.isDef() || !Op.getReg())
540 bool IsHiReg = HiOperand.isReg();
541 bool IsLoReg = LoOperand.isReg();
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCCodeEmitter.cpp | 187 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
203 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
216 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
233 assert(MI.getOperand(OpNo+1).isReg());
249 assert(MI.getOperand(OpNo+1).isReg());
276 if (MO.isReg()) {
|
| /external/llvm/lib/MC/ |
| MCInst.cpp | 22 else if (isReg())
|
| /external/llvm/lib/Target/XCore/InstPrinter/ |
| XCoreInstPrinter.cpp | 74 if (Op.isReg()) {
|
| /external/llvm/lib/Target/R600/ |
| SIInsertWaits.cpp | 138 if (!Op.isReg())
140 assert(Op.isReg() && "First LGKM operand must be a register!");
156 if (!Op.isReg())
175 if (I->isReg() && I->isUse())
184 if (!Op.isReg())
|
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 49 if (Op.isReg()) {
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 115 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
116 MI->getOperand(Op+2).isReg() &&
126 MI->getOperand(Op+4).isReg() &&
355 if (!MO.isReg()) return false;
|
