| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 224 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
229 { ISD::SRL, MVT::v16i8, 1 }, // psrlw.
234 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
258 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
263 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
268 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
279 { ISD::SDIV, MVT::v16i8, 16*20 },
283 { ISD::UDIV, MVT::v16i8, 16*20 },
373 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
377 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| X86FastISel.cpp | 280 case MVT::v16i8:
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 73 v16i8 = 22, // 16 x i8 enumerator in enum:llvm::MVT::SimpleValueType
211 return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 ||
271 case v16i8:
311 case v16i8:
389 case v16i8:
496 if (NumElements == 16) return MVT::v16i8;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 227 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
228 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
231 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
462 { ISD::VECTOR_SHUFFLE, MVT::v16i8, 2 }
517 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
518 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
519 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
520 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
|
| ARMISelDAGToDAG.cpp | [all...] |
| ARMISelLowering.cpp | 465 addQRTypeForNEON(MVT::v16i8);
579 // v8i8/v16i8 vcnt instruction.
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 68 DecodePALIGNRMask(MVT::v16i8,
152 DecodeUNPCKHMask(MVT::v16i8, ShuffleMask);
225 DecodeUNPCKLMask(MVT::v16i8, ShuffleMask);
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 140 case MVT::v16i8: return "v16i8";
203 case MVT::v16i8: return VectorType::get(Type::getInt8Ty(Context), 16);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 375 // We promote all shuffles to v16i8.
377 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
446 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
466 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
478 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
483 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
735 assert(N->getValueType(0) == MVT::v16i8 &&
[all...] |
| PPCISelDAGToDAG.cpp | 631 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
638 if (VecVT == MVT::v16i8)
652 if (VecVT == MVT::v16i8)
665 if (VecVT == MVT::v16i8)
694 // types (v16i8, v8i16, v4i32, and v4f32).
697 case MVT::v16i8:
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 81 case MVT::v16i8: return "MVT::v16i8";
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 65 addRegisterClass(MVT::v16i8, &AArch64::VPR128RegClass);
274 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
286 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 40 addRegisterClass(MVT::v16i8, &AMDGPU::SReg_128RegClass);
[all...] |
