| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 370 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
371 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
372 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
373 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
374 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
375 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
376 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
377 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
470 { ISD::SETCC, MVT::v2f64, 1 },
|
| X86ISelLowering.cpp | [all...] |
| X86FastISel.cpp | 271 case MVT::v2f64:
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 65 (int)MVT::v2f64,
93 (int)MVT::v2f64,
188 // we support loading/storing v2f64 but not operations on the type
189 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
190 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
191 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
192 setOperationAction(ISD::FP_ROUND_INREG, MVT::v2f64, Expand);
193 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
197 setOperationAction(ISD::TRUNCATE, MVT::v2f64, Expand);
198 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 37 // For the 2nd half of a v2f64, do not fail.
64 if (LocVT == MVT::v2f64 &&
86 // For the 2nd half of a v2f64, do not just fail.
118 if (LocVT == MVT::v2f64 &&
150 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
|
| ARMTargetTransformInfo.cpp | 187 { ISD::FP_ROUND, MVT::v2f64, 2 },
267 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
268 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
270 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
271 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
272 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
273 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
274 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
275 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
277 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }
[all...] |
| ARMISelLowering.cpp | 159 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
464 addQRTypeForNEON(MVT::v2f64);
470 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
474 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
475 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
476 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
479 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
480 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
484 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
487 setOperationAction(ISD::SETCC, MVT::v2f64, Expand)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 57 (int)MVT::v2f64,
82 (int)MVT::v2f64,
171 // we support loading/storing v2f64 but not operations on the type
172 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
173 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
174 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
175 setOperationAction(ISD::FP_ROUND_INREG, MVT::v2f64, Expand);
176 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
180 setOperationAction(ISD::TRUNCATE, MVT::v2f64, Expand);
181 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 65 (int)MVT::v2f64,
93 (int)MVT::v2f64,
188 // we support loading/storing v2f64 but not operations on the type
189 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
190 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
191 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
192 setOperationAction(ISD::FP_ROUND_INREG, MVT::v2f64, Expand);
193 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
197 setOperationAction(ISD::TRUNCATE, MVT::v2f64, Expand);
198 setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 101 v2f64 = 46, // 2 x f64 enumerator in enum:llvm::MVT::SimpleValueType
213 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
295 case v2f64:
337 case v2f64: return 2;
394 case v2f64: return 128;
532 if (NumElements == 2) return MVT::v2f64;
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 296 DecodeSHUFPMask(MVT::v2f64, MI->getOperand(MI->getNumOperands()-1).getImm(),
338 DecodeUNPCKLMask(MVT::v2f64, ShuffleMask);
374 DecodeUNPCKHMask(MVT::v2f64, ShuffleMask);
424 DecodePSHUFMask(MVT::v2f64, MI->getOperand(MI->getNumOperands()-1).getImm(),
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 164 case MVT::v2f64: return "v2f64";
227 case MVT::v2f64: return VectorType::get(Type::getDoubleTy(Context), 2);
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 105 case MVT::v2f64: return "MVT::v2f64";
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 65 case MVT::v2f64:
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 70 addRegisterClass(MVT::v2f64, &AArch64::VPR128RegClass);
283 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
294 setOperationAction(ISD::SETCC, MVT::v2f64, Custom);
[all...] |
