| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 158 setOperationAction(ISD::CTLZ, VT, Expand);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 224 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
225 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
226 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 161 // We have native support for a 64-bit CTLZ, via FLOGR.
162 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
163 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
[all...] |
| SystemZInstrInfo.td | [all...] |
| /external/llvm/docs/ |
| LangRef.rst | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 309 BSWAP, CTTZ, CTLZ, CTPOP,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| README.txt | 493 bits could perhaps be replaced by the target-independent ctlz and ctpop
|
| ARMISelLowering.cpp | 678 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
680 // These just redirect to CTTZ and CTLZ on ARM.
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopIdiomRecognize.cpp | 23 // ctpop, ctlz, cttz
[all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | 738 case Intrinsic::ctlz:
[all...] |
| /external/llvm/lib/IR/ |
| Verifier.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 474 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
483 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
484 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
490 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstr64Bit.td | 522 [(set i64:$rA, (ctlz i64:$rS))]>;
[all...] |
| PPCInstrInfo.td | [all...] |
| PPCISelLowering.cpp | 427 setOperationAction(ISD::CTLZ, VT, Expand);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.td | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCalls.cpp | 332 case Intrinsic::ctlz: {
[all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | 313 Value *F = CGM.getIntrinsic(Intrinsic::ctlz, ArgType);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.td | 516 [(set (i32 IntRegs:$dst), (ctlz (i32 IntRegs:$src1)))]>;
524 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 372 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
373 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | [all...] |
