1 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Stack allocation 12 //===----------------------------------------------------------------------===// 13 14 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 15 [(callseq_start timm:$amt)]>; 16 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 17 [(callseq_end timm:$amt1, timm:$amt2)]>; 18 19 let neverHasSideEffects = 1 in { 20 // Takes as input the value of the stack pointer after a dynamic allocation 21 // has been made. Sets the output to the address of the dynamically- 22 // allocated area itself, skipping the outgoing arguments. 23 // 24 // This expands to an LA or LAY instruction. We restrict the offset 25 // to the range of LA and keep the LAY range in reserve for when 26 // the size of the outgoing arguments is added. 27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 28 [(set GR64:$dst, dynalloc12only:$src)]>; 29 } 30 31 //===----------------------------------------------------------------------===// 32 // Control flow instructions 33 //===----------------------------------------------------------------------===// 34 35 // A return instruction. R1 is the condition-code mask (all 1s) 36 // and R2 is the target address, which is always stored in %r14. 37 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1, 38 R1 = 15, R2 = 14, isCodeGenOnly = 1 in { 39 def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>; 40 } 41 42 // Unconditional branches. R1 is the condition-code mask (all 1s). 43 let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in { 44 let isIndirectBranch = 1 in 45 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), 46 "br\t$R2", [(brind ADDR64:$R2)]>; 47 48 // An assembler extended mnemonic for BRC. 49 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", 50 [(br bb:$I2)]>; 51 52 // An assembler extended mnemonic for BRCL. (The extension is "G" 53 // rather than "L" because "JL" is "Jump if Less".) 54 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>; 55 } 56 57 // Conditional branches. It's easier for LLVM to handle these branches 58 // in their raw BRC/BRCL form, with the 4-bit condition-code mask being 59 // the first operand. It seems friendlier to use mnemonic forms like 60 // JE and JLH when writing out the assembly though. 61 let isBranch = 1, isTerminator = 1, Uses = [CC] in { 62 let isCodeGenOnly = 1, CCMaskFirst = 1 in { 63 def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1, 64 brtarget16:$I2), "j$R1\t$I2", 65 [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>; 66 def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1, 67 brtarget32:$I2), "jg$R1\t$I2", []>; 68 } 69 def AsmBRC : InstRI<0xA74, (outs), (ins uimm8zx4:$R1, brtarget16:$I2), 70 "brc\t$R1, $I2", []>; 71 def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2), 72 "brcl\t$R1, $I2", []>; 73 } 74 75 // Fused compare-and-branch instructions. As for normal branches, 76 // we handle these instructions internally in their raw CRJ-like form, 77 // but use assembly macros like CRJE when writing them out. 78 // 79 // These instructions do not use or clobber the condition codes. 80 // We nevertheless pretend that they clobber CC, so that we can lower 81 // them to separate comparisons and BRCLs if the branch ends up being 82 // out of range. 83 multiclass CompareBranches<Operand ccmask, string pos1, string pos2> { 84 let isBranch = 1, isTerminator = 1, Defs = [CC] in { 85 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 86 brtarget16:$RI4), 87 "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>; 88 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 89 brtarget16:$RI4), 90 "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>; 91 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3, 92 brtarget16:$RI4), 93 "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>; 94 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3, 95 brtarget16:$RI4), 96 "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>; 97 } 98 } 99 let isCodeGenOnly = 1 in 100 defm C : CompareBranches<cond4, "$M3", "">; 101 defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">; 102 103 // Define AsmParser mnemonics for each general condition-code mask 104 // (integer or floating-point) 105 multiclass CondExtendedMnemonic<bits<4> ccmask, string name> { 106 let R1 = ccmask in { 107 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), 108 "j"##name##"\t$I2", []>; 109 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), 110 "jg"##name##"\t$I2", []>; 111 } 112 def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>; 113 def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>; 114 def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>; 115 def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>; 116 def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>; 117 def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>; 118 } 119 defm AsmO : CondExtendedMnemonic<1, "o">; 120 defm AsmH : CondExtendedMnemonic<2, "h">; 121 defm AsmNLE : CondExtendedMnemonic<3, "nle">; 122 defm AsmL : CondExtendedMnemonic<4, "l">; 123 defm AsmNHE : CondExtendedMnemonic<5, "nhe">; 124 defm AsmLH : CondExtendedMnemonic<6, "lh">; 125 defm AsmNE : CondExtendedMnemonic<7, "ne">; 126 defm AsmE : CondExtendedMnemonic<8, "e">; 127 defm AsmNLH : CondExtendedMnemonic<9, "nlh">; 128 defm AsmHE : CondExtendedMnemonic<10, "he">; 129 defm AsmNL : CondExtendedMnemonic<11, "nl">; 130 defm AsmLE : CondExtendedMnemonic<12, "le">; 131 defm AsmNH : CondExtendedMnemonic<13, "nh">; 132 defm AsmNO : CondExtendedMnemonic<14, "no">; 133 134 // Define AsmParser mnemonics for each integer condition-code mask. 135 // This is like the list above, except that condition 3 is not possible 136 // and that the low bit of the mask is therefore always 0. This means 137 // that each condition has two names. Conditions "o" and "no" are not used. 138 // 139 // We don't make one of the two names an alias of the other because 140 // we need the custom parsing routines to select the correct register class. 141 multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> { 142 let M3 = ccmask in { 143 def CR : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, 144 brtarget16:$RI4), 145 "crj"##name##"\t$R1, $R2, $RI4", []>; 146 def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, 147 brtarget16:$RI4), 148 "cgrj"##name##"\t$R1, $R2, $RI4", []>; 149 def CI : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, 150 brtarget16:$RI4), 151 "cij"##name##"\t$R1, $I2, $RI4", []>; 152 def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, 153 brtarget16:$RI4), 154 "cgij"##name##"\t$R1, $I2, $RI4", []>; 155 } 156 } 157 multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2> 158 : IntCondExtendedMnemonicA<ccmask, name1> { 159 let isAsmParserOnly = 1 in 160 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>; 161 } 162 defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">; 163 defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">; 164 defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">; 165 defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">; 166 defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">; 167 defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">; 168 169 // Decrement a register and branch if it is nonzero. These don't clobber CC, 170 // but we might need to split long branches into sequences that do. 171 let Defs = [CC] in { 172 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 173 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 174 } 175 176 //===----------------------------------------------------------------------===// 177 // Select instructions 178 //===----------------------------------------------------------------------===// 179 180 def Select32 : SelectWrapper<GR32>; 181 def Select64 : SelectWrapper<GR64>; 182 183 defm CondStore8_32 : CondStores<GR32, nonvolatile_truncstorei8, 184 nonvolatile_anyextloadi8, bdxaddr20only>; 185 defm CondStore16_32 : CondStores<GR32, nonvolatile_truncstorei16, 186 nonvolatile_anyextloadi16, bdxaddr20only>; 187 defm CondStore32_32 : CondStores<GR32, nonvolatile_store, 188 nonvolatile_load, bdxaddr20only>; 189 190 defm CondStore8 : CondStores<GR64, nonvolatile_truncstorei8, 191 nonvolatile_anyextloadi8, bdxaddr20only>; 192 defm CondStore16 : CondStores<GR64, nonvolatile_truncstorei16, 193 nonvolatile_anyextloadi16, bdxaddr20only>; 194 defm CondStore32 : CondStores<GR64, nonvolatile_truncstorei32, 195 nonvolatile_anyextloadi32, bdxaddr20only>; 196 defm CondStore64 : CondStores<GR64, nonvolatile_store, 197 nonvolatile_load, bdxaddr20only>; 198 199 //===----------------------------------------------------------------------===// 200 // Call instructions 201 //===----------------------------------------------------------------------===// 202 203 // The definitions here are for the call-clobbered registers. 204 let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D, 205 F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D, CC], 206 R1 = 14, isCodeGenOnly = 1 in { 207 def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$I2, variable_ops), 208 "bras\t%r14, $I2", []>; 209 def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$I2, variable_ops), 210 "brasl\t%r14, $I2", [(z_call pcrel32call:$I2)]>; 211 def BASR : InstRR<0x0D, (outs), (ins ADDR64:$R2, variable_ops), 212 "basr\t%r14, $R2", [(z_call ADDR64:$R2)]>; 213 } 214 215 // Define the general form of the call instructions for the asm parser. 216 // These instructions don't hard-code %r14 as the return address register. 217 def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2), 218 "bras\t$R1, $I2", []>; 219 def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2), 220 "brasl\t$R1, $I2", []>; 221 def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2), 222 "basr\t$R1, $R2", []>; 223 224 //===----------------------------------------------------------------------===// 225 // Move instructions 226 //===----------------------------------------------------------------------===// 227 228 // Register moves. 229 let neverHasSideEffects = 1 in { 230 def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>; 231 def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>; 232 } 233 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 234 def LTR : UnaryRR <"lt", 0x12, null_frag, GR32, GR32>; 235 def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>; 236 } 237 238 // Move on condition. 239 let isCodeGenOnly = 1, Uses = [CC] in { 240 def LOCR : CondUnaryRRF<"loc", 0xB9F2, GR32, GR32>; 241 def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>; 242 } 243 let Uses = [CC] in { 244 def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>; 245 def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>; 246 } 247 248 // Immediate moves. 249 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 250 isReMaterializable = 1 in { 251 // 16-bit sign-extended immediates. 252 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 253 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 254 255 // Other 16-bit immediates. 256 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 257 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 258 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 259 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 260 261 // 32-bit immediates. 262 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 263 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 264 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 265 } 266 267 // Register loads. 268 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 269 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 270 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 271 272 // These instructions are split after register allocation, so we don't 273 // want a custom inserter. 274 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 275 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 276 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 277 } 278 } 279 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 280 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 281 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 282 } 283 284 let canFoldAsLoad = 1 in { 285 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 286 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 287 } 288 289 // Load on condition. 290 let isCodeGenOnly = 1, Uses = [CC] in { 291 def LOC : CondUnaryRSY<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; 292 def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>; 293 } 294 let Uses = [CC] in { 295 def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>; 296 def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>; 297 } 298 299 // Register stores. 300 let SimpleBDXStore = 1 in { 301 let isCodeGenOnly = 1 in 302 defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 303 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 304 305 // These instructions are split after register allocation, so we don't 306 // want a custom inserter. 307 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 308 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 309 [(store GR128:$src, bdxaddr20only128:$dst)]>; 310 } 311 } 312 let isCodeGenOnly = 1 in 313 def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 314 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 315 316 // Store on condition. 317 let isCodeGenOnly = 1, Uses = [CC] in { 318 def STOC32 : CondStoreRSY<"stoc", 0xEBF3, GR32, 4>; 319 def STOC : CondStoreRSY<"stoc", 0xEBF3, GR64, 4>; 320 def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>; 321 } 322 let Uses = [CC] in { 323 def AsmSTOC : AsmCondStoreRSY<"stoc", 0xEBF3, GR32, 4>; 324 def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>; 325 } 326 327 // 8-bit immediate stores to 8-bit fields. 328 defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 329 330 // 16-bit immediate stores to 16-, 32- or 64-bit fields. 331 def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 332 def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 333 def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 334 335 // Memory-to-memory moves. 336 let mayLoad = 1, mayStore = 1 in 337 def MVC : InstSS<0xD2, (outs), (ins bdladdr12onlylen8:$BDL1, 338 bdaddr12only:$BD2), 339 "mvc\t$BDL1, $BD2", []>; 340 341 let mayLoad = 1, mayStore = 1, usesCustomInserter = 1 in 342 def MVCWrapper : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 343 imm32len8:$length), 344 [(z_mvc bdaddr12only:$dest, bdaddr12only:$src, 345 imm32len8:$length)]>; 346 347 defm LoadStore8_32 : MVCLoadStore<anyextloadi8, truncstorei8, i32, 348 MVCWrapper, 1>; 349 defm LoadStore16_32 : MVCLoadStore<anyextloadi16, truncstorei16, i32, 350 MVCWrapper, 2>; 351 defm LoadStore32_32 : MVCLoadStore<load, store, i32, MVCWrapper, 4>; 352 353 defm LoadStore8 : MVCLoadStore<anyextloadi8, truncstorei8, i64, 354 MVCWrapper, 1>; 355 defm LoadStore16 : MVCLoadStore<anyextloadi16, truncstorei16, i64, 356 MVCWrapper, 2>; 357 defm LoadStore32 : MVCLoadStore<anyextloadi32, truncstorei32, i64, 358 MVCWrapper, 4>; 359 defm LoadStore64 : MVCLoadStore<load, store, i64, MVCWrapper, 8>; 360 361 //===----------------------------------------------------------------------===// 362 // Sign extensions 363 //===----------------------------------------------------------------------===// 364 365 // 32-bit extensions from registers. 366 let neverHasSideEffects = 1 in { 367 def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>; 368 def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>; 369 } 370 371 // 64-bit extensions from registers. 372 let neverHasSideEffects = 1 in { 373 def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>; 374 def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>; 375 def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>; 376 } 377 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 378 def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR64>; 379 380 // Match 32-to-64-bit sign extensions in which the source is already 381 // in a 64-bit register. 382 def : Pat<(sext_inreg GR64:$src, i32), 383 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; 384 385 // 32-bit extensions from memory. 386 def LB : UnaryRXY<"lb", 0xE376, sextloadi8, GR32, 1>; 387 defm LH : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32, 2>; 388 def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_sextloadi16, GR32>; 389 390 // 64-bit extensions from memory. 391 def LGB : UnaryRXY<"lgb", 0xE377, sextloadi8, GR64, 1>; 392 def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64, 2>; 393 def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64, 4>; 394 def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>; 395 def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>; 396 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 397 def LTGF : UnaryRXY<"ltgf", 0xE332, sextloadi32, GR64, 4>; 398 399 // If the sign of a load-extend operation doesn't matter, use the signed ones. 400 // There's not really much to choose between the sign and zero extensions, 401 // but LH is more compact than LLH for small offsets. 402 def : Pat<(i32 (extloadi8 bdxaddr20only:$src)), (LB bdxaddr20only:$src)>; 403 def : Pat<(i32 (extloadi16 bdxaddr12pair:$src)), (LH bdxaddr12pair:$src)>; 404 def : Pat<(i32 (extloadi16 bdxaddr20pair:$src)), (LHY bdxaddr20pair:$src)>; 405 406 def : Pat<(i64 (extloadi8 bdxaddr20only:$src)), (LGB bdxaddr20only:$src)>; 407 def : Pat<(i64 (extloadi16 bdxaddr20only:$src)), (LGH bdxaddr20only:$src)>; 408 def : Pat<(i64 (extloadi32 bdxaddr20only:$src)), (LGF bdxaddr20only:$src)>; 409 410 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 411 // However, BDXs have two extra operands and are therefore 6 units more 412 // complex. 413 let AddedComplexity = 7 in { 414 def : Pat<(i32 (extloadi16 pcrel32:$src)), (LHRL pcrel32:$src)>; 415 def : Pat<(i64 (extloadi16 pcrel32:$src)), (LGHRL pcrel32:$src)>; 416 } 417 418 //===----------------------------------------------------------------------===// 419 // Zero extensions 420 //===----------------------------------------------------------------------===// 421 422 // 32-bit extensions from registers. 423 let neverHasSideEffects = 1 in { 424 def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>; 425 def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>; 426 } 427 428 // 64-bit extensions from registers. 429 let neverHasSideEffects = 1 in { 430 def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>; 431 def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>; 432 def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>; 433 } 434 435 // Match 32-to-64-bit zero extensions in which the source is already 436 // in a 64-bit register. 437 def : Pat<(and GR64:$src, 0xffffffff), 438 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; 439 440 // 32-bit extensions from memory. 441 def LLC : UnaryRXY<"llc", 0xE394, zextloadi8, GR32, 1>; 442 def LLH : UnaryRXY<"llh", 0xE395, zextloadi16, GR32, 2>; 443 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_zextloadi16, GR32>; 444 445 // 64-bit extensions from memory. 446 def LLGC : UnaryRXY<"llgc", 0xE390, zextloadi8, GR64, 1>; 447 def LLGH : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64, 2>; 448 def LLGF : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64, 4>; 449 def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_zextloadi16, GR64>; 450 def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_zextloadi32, GR64>; 451 452 //===----------------------------------------------------------------------===// 453 // Truncations 454 //===----------------------------------------------------------------------===// 455 456 // Truncations of 64-bit registers to 32-bit registers. 457 def : Pat<(i32 (trunc GR64:$src)), 458 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>; 459 460 // Truncations of 32-bit registers to memory. 461 let isCodeGenOnly = 1 in { 462 defm STC32 : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 463 defm STH32 : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 464 def STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 465 } 466 467 // Truncations of 64-bit registers to memory. 468 defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR64, 1>; 469 defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64, 2>; 470 def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>; 471 defm ST : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64, 4>; 472 def STRL : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>; 473 474 //===----------------------------------------------------------------------===// 475 // Multi-register moves 476 //===----------------------------------------------------------------------===// 477 478 // Multi-register loads. 479 def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 480 481 // Multi-register stores. 482 def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 483 484 //===----------------------------------------------------------------------===// 485 // Byte swaps 486 //===----------------------------------------------------------------------===// 487 488 // Byte-swapping register moves. 489 let neverHasSideEffects = 1 in { 490 def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>; 491 def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>; 492 } 493 494 // Byte-swapping loads. Unlike normal loads, these instructions are 495 // allowed to access storage more than once. 496 def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>; 497 def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>; 498 499 // Likewise byte-swapping stores. 500 def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>; 501 def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>, 502 GR64, 8>; 503 504 //===----------------------------------------------------------------------===// 505 // Load address instructions 506 //===----------------------------------------------------------------------===// 507 508 // Load BDX-style addresses. 509 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1, 510 DispKey = "la" in { 511 let DispSize = "12" in 512 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2), 513 "la\t$R1, $XBD2", 514 [(set GR64:$R1, laaddr12pair:$XBD2)]>; 515 let DispSize = "20" in 516 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2), 517 "lay\t$R1, $XBD2", 518 [(set GR64:$R1, laaddr20pair:$XBD2)]>; 519 } 520 521 // Load a PC-relative address. There's no version of this instruction 522 // with a 16-bit offset, so there's no relaxation. 523 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 524 isReMaterializable = 1 in { 525 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2), 526 "larl\t$R1, $I2", 527 [(set GR64:$R1, pcrel32:$I2)]>; 528 } 529 530 //===----------------------------------------------------------------------===// 531 // Negation 532 //===----------------------------------------------------------------------===// 533 534 let Defs = [CC] in { 535 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 536 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>; 537 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>; 538 } 539 let CCValues = 0xE, CompareZeroCCMask = 0xE in 540 def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>; 541 } 542 defm : SXU<ineg, LCGFR>; 543 544 //===----------------------------------------------------------------------===// 545 // Insertion 546 //===----------------------------------------------------------------------===// 547 548 let isCodeGenOnly = 1 in 549 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8, 1>; 550 defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8, 1>; 551 552 defm : InsertMem<"inserti8", IC32, GR32, zextloadi8, bdxaddr12pair>; 553 defm : InsertMem<"inserti8", IC32Y, GR32, zextloadi8, bdxaddr20pair>; 554 555 defm : InsertMem<"inserti8", IC, GR64, zextloadi8, bdxaddr12pair>; 556 defm : InsertMem<"inserti8", ICY, GR64, zextloadi8, bdxaddr20pair>; 557 558 // Insertions of a 16-bit immediate, leaving other bits unaffected. 559 // We don't have or_as_insert equivalents of these operations because 560 // OI is available instead. 561 let isCodeGenOnly = 1 in { 562 def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 563 def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 564 } 565 def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>; 566 def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>; 567 def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>; 568 def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>; 569 570 // ...likewise for 32-bit immediates. For GR32s this is a general 571 // full-width move. (We use IILF rather than something like LLILF 572 // for 32-bit moves because IILF leaves the upper 32 bits of the 573 // GR64 unchanged.) 574 let isCodeGenOnly = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 575 isReMaterializable = 1 in { 576 def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 577 } 578 def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>; 579 def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>; 580 581 // An alternative model of inserthf, with the first operand being 582 // a zero-extended value. 583 def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 584 (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit), 585 imm64hf32:$imm)>; 586 587 //===----------------------------------------------------------------------===// 588 // Addition 589 //===----------------------------------------------------------------------===// 590 591 // Plain addition. 592 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 593 // Addition of a register. 594 let isCommutable = 1 in { 595 defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>; 596 defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>; 597 } 598 def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>; 599 600 // Addition of signed 16-bit immediates. 601 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>; 602 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>; 603 604 // Addition of signed 32-bit immediates. 605 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; 606 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>; 607 608 // Addition of memory. 609 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16, 2>; 610 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>; 611 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32, 4>; 612 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>; 613 614 // Addition to memory. 615 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 616 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 617 } 618 defm : SXB<add, GR64, AGFR>; 619 620 // Addition producing a carry. 621 let Defs = [CC] in { 622 // Addition of a register. 623 let isCommutable = 1 in { 624 defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>; 625 defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>; 626 } 627 def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>; 628 629 // Addition of signed 16-bit immediates. 630 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>, 631 Requires<[FeatureDistinctOps]>; 632 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>, 633 Requires<[FeatureDistinctOps]>; 634 635 // Addition of unsigned 32-bit immediates. 636 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; 637 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; 638 639 // Addition of memory. 640 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>; 641 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32, 4>; 642 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>; 643 } 644 defm : ZXB<addc, GR64, ALGFR>; 645 646 // Addition producing and using a carry. 647 let Defs = [CC], Uses = [CC] in { 648 // Addition of a register. 649 def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>; 650 def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>; 651 652 // Addition of memory. 653 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>; 654 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>; 655 } 656 657 //===----------------------------------------------------------------------===// 658 // Subtraction 659 //===----------------------------------------------------------------------===// 660 661 // Plain substraction. Although immediate forms exist, we use the 662 // add-immediate instruction instead. 663 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 664 // Subtraction of a register. 665 defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>; 666 def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>; 667 defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>; 668 669 // Subtraction of memory. 670 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16, 2>; 671 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>; 672 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32, 4>; 673 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>; 674 } 675 defm : SXB<sub, GR64, SGFR>; 676 677 // Subtraction producing a carry. 678 let Defs = [CC] in { 679 // Subtraction of a register. 680 defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>; 681 def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>; 682 defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>; 683 684 // Subtraction of unsigned 32-bit immediates. These don't match 685 // subc because we prefer addc for constants. 686 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>; 687 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>; 688 689 // Subtraction of memory. 690 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>; 691 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, zextloadi32, 4>; 692 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>; 693 } 694 defm : ZXB<subc, GR64, SLGFR>; 695 696 // Subtraction producing and using a carry. 697 let Defs = [CC], Uses = [CC] in { 698 // Subtraction of a register. 699 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>; 700 def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>; 701 702 // Subtraction of memory. 703 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>; 704 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>; 705 } 706 707 //===----------------------------------------------------------------------===// 708 // AND 709 //===----------------------------------------------------------------------===// 710 711 let Defs = [CC] in { 712 // ANDs of a register. 713 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 714 defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>; 715 defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>; 716 } 717 718 let isConvertibleToThreeAddress = 1 in { 719 // ANDs of a 16-bit immediate, leaving other bits unaffected. 720 // The CC result only reflects the 16-bit field, not the full register. 721 let isCodeGenOnly = 1 in { 722 def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 723 def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 724 } 725 def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>; 726 def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>; 727 def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>; 728 def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>; 729 730 // ANDs of a 32-bit immediate, leaving other bits unaffected. 731 // The CC result only reflects the 32-bit field, which means we can 732 // use it as a zero indicator for i32 operations but not otherwise. 733 let isCodeGenOnly = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in 734 def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 735 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>; 736 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>; 737 } 738 739 // ANDs of memory. 740 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 741 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>; 742 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 743 } 744 745 // AND to memory 746 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>; 747 } 748 defm : RMWIByte<and, bdaddr12pair, NI>; 749 defm : RMWIByte<and, bdaddr20pair, NIY>; 750 751 //===----------------------------------------------------------------------===// 752 // OR 753 //===----------------------------------------------------------------------===// 754 755 let Defs = [CC] in { 756 // ORs of a register. 757 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 758 defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>; 759 defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>; 760 } 761 762 // ORs of a 16-bit immediate, leaving other bits unaffected. 763 // The CC result only reflects the 16-bit field, not the full register. 764 let isCodeGenOnly = 1 in { 765 def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 766 def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 767 } 768 def OILL : BinaryRI<"oill", 0xA5B, or, GR64, imm64ll16>; 769 def OILH : BinaryRI<"oilh", 0xA5A, or, GR64, imm64lh16>; 770 def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>; 771 def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>; 772 773 // ORs of a 32-bit immediate, leaving other bits unaffected. 774 // The CC result only reflects the 32-bit field, which means we can 775 // use it as a zero indicator for i32 operations but not otherwise. 776 let isCodeGenOnly = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in 777 def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 778 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>; 779 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>; 780 781 // ORs of memory. 782 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 783 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>; 784 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>; 785 } 786 787 // OR to memory 788 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>; 789 } 790 defm : RMWIByte<or, bdaddr12pair, OI>; 791 defm : RMWIByte<or, bdaddr20pair, OIY>; 792 793 //===----------------------------------------------------------------------===// 794 // XOR 795 //===----------------------------------------------------------------------===// 796 797 let Defs = [CC] in { 798 // XORs of a register. 799 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 800 defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>; 801 defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>; 802 } 803 804 // XORs of a 32-bit immediate, leaving other bits unaffected. 805 // The CC result only reflects the 32-bit field, which means we can 806 // use it as a zero indicator for i32 operations but not otherwise. 807 let isCodeGenOnly = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in 808 def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 809 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>; 810 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>; 811 812 // XORs of memory. 813 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 814 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>; 815 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>; 816 } 817 818 // XOR to memory 819 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>; 820 } 821 defm : RMWIByte<xor, bdaddr12pair, XI>; 822 defm : RMWIByte<xor, bdaddr20pair, XIY>; 823 824 //===----------------------------------------------------------------------===// 825 // Multiplication 826 //===----------------------------------------------------------------------===// 827 828 // Multiplication of a register. 829 let isCommutable = 1 in { 830 def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>; 831 def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>; 832 } 833 def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>; 834 defm : SXB<mul, GR64, MSGFR>; 835 836 // Multiplication of a signed 16-bit immediate. 837 def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 838 def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 839 840 // Multiplication of a signed 32-bit immediate. 841 def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 842 def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 843 844 // Multiplication of memory. 845 defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, sextloadi16, 2>; 846 defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 847 def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, sextloadi32, 4>; 848 def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 849 850 // Multiplication of a register, producing two results. 851 def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>; 852 853 // Multiplication of memory, producing two results. 854 def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>; 855 856 //===----------------------------------------------------------------------===// 857 // Division and remainder 858 //===----------------------------------------------------------------------===// 859 860 // Division and remainder, from registers. 861 def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>; 862 def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>; 863 def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>; 864 def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>; 865 866 // Division and remainder, from memory. 867 def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>; 868 def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>; 869 def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>; 870 def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>; 871 872 //===----------------------------------------------------------------------===// 873 // Shifts 874 //===----------------------------------------------------------------------===// 875 876 // Shift left. 877 let neverHasSideEffects = 1 in { 878 defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>; 879 def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>; 880 } 881 882 // Logical shift right. 883 let neverHasSideEffects = 1 in { 884 defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>; 885 def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>; 886 } 887 888 // Arithmetic shift right. 889 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 890 defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>; 891 def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>; 892 } 893 894 // Rotate left. 895 let neverHasSideEffects = 1 in { 896 def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32>; 897 def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>; 898 } 899 900 // Rotate second operand left and inserted selected bits into first operand. 901 // These can act like 32-bit operands provided that the constant start and 902 // end bits (operands 2 and 3) are in the range [32, 64). 903 let Defs = [CC] in { 904 let isCodeGenOnly = 1 in 905 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 906 let CCValues = 0xE, CompareZeroCCMask = 0xE in 907 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 908 } 909 910 // Forms of RISBG that only affect one word of the destination register. 911 // They do not set CC. 912 let isCodeGenOnly = 1 in 913 def RISBLG32 : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR32>, 914 Requires<[FeatureHighWord]>; 915 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GR64, GR64>, 916 Requires<[FeatureHighWord]>; 917 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR64, GR64>, 918 Requires<[FeatureHighWord]>; 919 920 // Rotate second operand left and perform a logical operation with selected 921 // bits of the first operand. The CC result only describes the selected bits, 922 // so isn't useful for a full comparison against zero. 923 let Defs = [CC] in { 924 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 925 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 926 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 927 } 928 929 //===----------------------------------------------------------------------===// 930 // Comparison 931 //===----------------------------------------------------------------------===// 932 933 // Signed comparisons. 934 let Defs = [CC], CCValues = 0xE in { 935 // Comparison with a register. 936 def CR : CompareRR <"c", 0x19, z_cmp, GR32, GR32>; 937 def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>; 938 def CGR : CompareRRE<"cg", 0xB920, z_cmp, GR64, GR64>; 939 940 // Comparison with a signed 16-bit immediate. 941 def CHI : CompareRI<"chi", 0xA7E, z_cmp, GR32, imm32sx16>; 942 def CGHI : CompareRI<"cghi", 0xA7F, z_cmp, GR64, imm64sx16>; 943 944 // Comparison with a signed 32-bit immediate. 945 def CFI : CompareRIL<"cfi", 0xC2D, z_cmp, GR32, simm32>; 946 def CGFI : CompareRIL<"cgfi", 0xC2C, z_cmp, GR64, imm64sx32>; 947 948 // Comparison with memory. 949 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_cmp, GR32, sextloadi16, 2>; 950 defm C : CompareRXPair<"c", 0x59, 0xE359, z_cmp, GR32, load, 4>; 951 def CGH : CompareRXY<"cgh", 0xE334, z_cmp, GR64, sextloadi16, 2>; 952 def CGF : CompareRXY<"cgf", 0xE330, z_cmp, GR64, sextloadi32, 4>; 953 def CG : CompareRXY<"cg", 0xE320, z_cmp, GR64, load, 8>; 954 def CHRL : CompareRILPC<"chrl", 0xC65, z_cmp, GR32, aligned_sextloadi16>; 955 def CRL : CompareRILPC<"crl", 0xC6D, z_cmp, GR32, aligned_load>; 956 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_cmp, GR64, aligned_sextloadi16>; 957 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_cmp, GR64, aligned_sextloadi32>; 958 def CGRL : CompareRILPC<"cgrl", 0xC68, z_cmp, GR64, aligned_load>; 959 960 // Comparison between memory and a signed 16-bit immediate. 961 def CHHSI : CompareSIL<"chhsi", 0xE554, z_cmp, sextloadi16, imm32sx16>; 962 def CHSI : CompareSIL<"chsi", 0xE55C, z_cmp, load, imm32sx16>; 963 def CGHSI : CompareSIL<"cghsi", 0xE558, z_cmp, load, imm64sx16>; 964 } 965 defm : SXB<z_cmp, GR64, CGFR>; 966 967 // Unsigned comparisons. 968 let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 969 // Comparison with a register. 970 def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>; 971 def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>; 972 def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>; 973 974 // Comparison with a signed 32-bit immediate. 975 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 976 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 977 978 // Comparison with memory. 979 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 980 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, zextloadi32, 4>; 981 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 982 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 983 aligned_zextloadi16>; 984 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 985 aligned_load>; 986 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 987 aligned_zextloadi16>; 988 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 989 aligned_zextloadi32>; 990 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 991 aligned_load>; 992 993 // Comparison between memory and an unsigned 8-bit immediate. 994 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, zextloadi8, imm32zx8>; 995 996 // Comparison between memory and an unsigned 16-bit immediate. 997 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, zextloadi16, imm32zx16>; 998 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 999 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1000 } 1001 defm : ZXB<z_ucmp, GR64, CLGFR>; 1002 1003 //===----------------------------------------------------------------------===// 1004 // Atomic operations 1005 //===----------------------------------------------------------------------===// 1006 1007 def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1008 def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1009 def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1010 1011 def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1012 def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1013 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1014 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1015 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1016 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1017 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1018 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1019 1020 def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1021 def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1022 def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1023 1024 def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1025 def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1026 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1027 def ATOMIC_LOAD_NILL32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>; 1028 def ATOMIC_LOAD_NILH32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>; 1029 def ATOMIC_LOAD_NILF32 : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1030 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1031 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>; 1032 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>; 1033 def ATOMIC_LOAD_NIHL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>; 1034 def ATOMIC_LOAD_NIHH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>; 1035 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>; 1036 def ATOMIC_LOAD_NIHF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>; 1037 1038 def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1039 def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1040 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1041 def ATOMIC_LOAD_OILL32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1042 def ATOMIC_LOAD_OILH32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1043 def ATOMIC_LOAD_OILF32 : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1044 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1045 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1046 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1047 def ATOMIC_LOAD_OIHL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1048 def ATOMIC_LOAD_OIHH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1049 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1050 def ATOMIC_LOAD_OIHF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1051 1052 def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1053 def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1054 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1055 def ATOMIC_LOAD_XILF32 : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1056 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1057 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1058 def ATOMIC_LOAD_XIHF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1059 1060 def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1061 def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1062 imm32lh16c>; 1063 def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1064 def ATOMIC_LOAD_NILL32i : AtomicLoadBinaryImm32<atomic_load_nand_32, 1065 imm32ll16c>; 1066 def ATOMIC_LOAD_NILH32i : AtomicLoadBinaryImm32<atomic_load_nand_32, 1067 imm32lh16c>; 1068 def ATOMIC_LOAD_NILF32i : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1069 def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1070 def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm64<atomic_load_nand_64, 1071 imm64ll16c>; 1072 def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm64<atomic_load_nand_64, 1073 imm64lh16c>; 1074 def ATOMIC_LOAD_NIHLi : AtomicLoadBinaryImm64<atomic_load_nand_64, 1075 imm64hl16c>; 1076 def ATOMIC_LOAD_NIHHi : AtomicLoadBinaryImm64<atomic_load_nand_64, 1077 imm64hh16c>; 1078 def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm64<atomic_load_nand_64, 1079 imm64lf32c>; 1080 def ATOMIC_LOAD_NIHFi : AtomicLoadBinaryImm64<atomic_load_nand_64, 1081 imm64hf32c>; 1082 1083 def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1084 def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1085 def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1086 1087 def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1088 def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1089 def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1090 1091 def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1092 def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1093 def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1094 1095 def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1096 def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1097 def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1098 1099 def ATOMIC_CMP_SWAPW 1100 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1101 ADDR32:$bitshift, ADDR32:$negbitshift, 1102 uimm32:$bitsize), 1103 [(set GR32:$dst, 1104 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1105 ADDR32:$bitshift, ADDR32:$negbitshift, 1106 uimm32:$bitsize))]> { 1107 let Defs = [CC]; 1108 let mayLoad = 1; 1109 let mayStore = 1; 1110 let usesCustomInserter = 1; 1111 } 1112 1113 let Defs = [CC] in { 1114 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>; 1115 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>; 1116 } 1117 1118 //===----------------------------------------------------------------------===// 1119 // Miscellaneous Instructions. 1120 //===----------------------------------------------------------------------===// 1121 1122 // Read a 32-bit access register into a GR32. As with all GR32 operations, 1123 // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1124 // when a 64-bit address is stored in a pair of access registers. 1125 def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2), 1126 "ear\t$R1, $R2", 1127 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>; 1128 1129 // Find leftmost one, AKA count leading zeros. The instruction actually 1130 // returns a pair of GR64s, the first giving the number of leading zeros 1131 // and the second giving a copy of the source with the leftmost one bit 1132 // cleared. We only use the first result here. 1133 let Defs = [CC] in { 1134 def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>; 1135 } 1136 def : Pat<(ctlz GR64:$src), 1137 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>; 1138 1139 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 1140 def : Pat<(i64 (anyext GR32:$src)), 1141 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>; 1142 1143 // There are no 32-bit equivalents of LLILL and LLILH, so use a full 1144 // 64-bit move followed by a subreg. This preserves the invariant that 1145 // all GR32 operations only modify the low 32 bits. 1146 def : Pat<(i32 imm32ll16:$src), 1147 (EXTRACT_SUBREG (LLILL (LL16 imm:$src)), subreg_32bit)>; 1148 def : Pat<(i32 imm32lh16:$src), 1149 (EXTRACT_SUBREG (LLILH (LH16 imm:$src)), subreg_32bit)>; 1150 1151 // Extend GR32s and GR64s to GR128s. 1152 let usesCustomInserter = 1 in { 1153 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1154 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>; 1155 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1156 } 1157 1158 //===----------------------------------------------------------------------===// 1159 // Peepholes. 1160 //===----------------------------------------------------------------------===// 1161 1162 // Use AL* for GR64 additions of unsigned 32-bit values. 1163 defm : ZXB<add, GR64, ALGFR>; 1164 def : Pat<(add GR64:$src1, imm64zx32:$src2), 1165 (ALGFI GR64:$src1, imm64zx32:$src2)>; 1166 def : Pat<(add GR64:$src1, (zextloadi32 bdxaddr20only:$addr)), 1167 (ALGF GR64:$src1, bdxaddr20only:$addr)>; 1168 1169 // Use SL* for GR64 subtractions of unsigned 32-bit values. 1170 defm : ZXB<sub, GR64, SLGFR>; 1171 def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1172 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1173 def : Pat<(sub GR64:$src1, (zextloadi32 bdxaddr20only:$addr)), 1174 (SLGF GR64:$src1, bdxaddr20only:$addr)>; 1175 1176 // Optimize sign-extended 1/0 selects to -1/0 selects. This is important 1177 // for vector legalization. 1178 def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid, uimm8zx4:$cc)), 1179 (i32 31)), 1180 (i32 31)), 1181 (Select32 (LHI -1), (LHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>; 1182 def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid, 1183 uimm8zx4:$cc)))), 1184 (i32 63)), 1185 (i32 63)), 1186 (Select64 (LGHI -1), (LGHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>; 1187
