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  /bionic/libc/arch-arm/cortex-a15/bionic/
memcpy_base.S 215 // than loads that cross a cacheline boundary.
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
brw_urb.c 251 /* erratum: URB_FENCE must not cross a 64byte cacheline */
  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_urb.c 251 /* erratum: URB_FENCE must not cross a 64byte cacheline */
  /external/kernel-headers/original/linux/
blkdev.h 126 * try to put the fields that are referenced together in the same cacheline
319 * Together with queue_head for cacheline sharing
mmzone.h 258 * give them a chance of being in the same cacheline.
283 * Right now a zonelist takes up less than a cacheline. We never
skbuff.h 991 * perhaps setting it to a cacheline in size (since that will maintain
992 * cacheline alignment of the DMA). It must be a power of 2.
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  /libcore/luni/src/main/java/java/util/concurrent/
Exchanger.java 128 * writing, there is no way to determine cacheline size, we define
229 * in the arena. 1 << ASHIFT should be at least cacheline size.
  /external/stressapptest/src/
sat.cc 1024 "cacheline's member\n"
    [all...]
os.cc 214 // We need to flush the cacheline here.
  /external/chromium_org/third_party/libwebp/dec/
vp8i.h 95 // With this layout, BPS (=Bytes Per Scan-line) is one cacheline size.
  /external/chromium_org/third_party/tcmalloc/chromium/src/
thread_cache.h 339 // Ensure that this class is cacheline-aligned. This is critical for
  /external/chromium_org/third_party/tcmalloc/vendor/src/
thread_cache.h 316 // Ensure that this class is cacheline-aligned. This is critical for
  /external/webp/src/dec/
vp8i.h 95 // With this layout, BPS (=Bytes Per Scan-line) is one cacheline size.
  /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/
unistd_64.h 14 /* at least 8 syscall per cacheline */
  /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/asm/
unistd_64.h 14 /* at least 8 syscall per cacheline */
  /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/asm/
unistd_64.h 14 /* at least 8 syscall per cacheline */
  /external/pixman/pixman/
pixman-arm-simd-asm.h 34 * * an inner loop section, where each time a cacheline of data is
35 * processed, another cacheline is preloaded (the exact distance ahead is
  /external/chromium_org/third_party/mesa/src/src/gallium/docs/
d3d11ddi.txt 106 * Gallium could do something similar to be able to put the private data inline into state tracker objects: this would allow them to fit in the same cacheline and improve performance
  /external/kernel-headers/original/asm-x86/
processor_32.h 336 * pads the TSS to be cacheline-aligned (size is 0x100)
  /external/mesa3d/src/gallium/docs/
d3d11ddi.txt 106 * Gallium could do something similar to be able to put the private data inline into state tracker objects: this would allow them to fit in the same cacheline and improve performance
  /external/pixman/test/
lowlevel-blt-bench.c 39 * that it's a number that's an integer divisor of both cacheline
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  /external/chromium_org/third_party/jemalloc/chromium/
jemalloc.c 518 #define CACHELINE ((size_t)(1U << CACHELINE_2POW))
762 # define MALLOC_RTREE_NODESIZE CACHELINE
1130 * pages are carved up in cacheline-size quanta, so that there is no chance of
    [all...]
  /external/chromium_org/third_party/jemalloc/vendor/
jemalloc.c 511 #define CACHELINE ((size_t)(1U << CACHELINE_2POW))
755 # define MALLOC_RTREE_NODESIZE CACHELINE
1123 * pages are carved up in cacheline-size quanta, so that there is no chance of
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/state_trackers/d3d1x/gd3d11/
d3d11_context.h     [all...]
  /external/mesa3d/src/gallium/state_trackers/d3d1x/gd3d11/
d3d11_context.h     [all...]

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