| /external/compiler-rt/test/timing/ |
| floatdixf.c | 44 printf("%16s: %f cycles.\n", LIBSTRING, bestTime / (double) INPUT_SIZE);
|
| floatundidf.c | 41 printf("%16s: %f cycles.\n", LIBSTRING, bestTime / (double) INPUT_SIZE);
|
| floatundisf.c | 44 printf("%16s: %f cycles.\n", LIBSTRING, bestTime / (double) INPUT_SIZE);
|
| floatundixf.c | 44 printf("%16s: %f cycles.\n", LIBSTRING, bestTime / (double) INPUT_SIZE);
|
| /external/dropbear/libtommath/logs/ |
| graphs.dem | 3 set ylabel "Cycles per Operation"
|
| /external/llvm/include/llvm/CodeGen/ |
| ScoreboardHazardRecognizer.h | 37 // Scoreboard always counts cycles in forward execution order. If used by a
38 // bottom-up scheduler, then the scoreboard cycles are the inverse of the
39 // scheduler's cycles.
43 // The maximum number of cycles monitored by the Scoreboard. This
|
| MachineTraceMetrics.h | 36 // cycles required to execute the trace when execution is limited by data
38 // of cycles required to execute all instructions in the trace when ignoring
41 // Every instruction in the current block has a slack - the number of cycles
110 /// Get the scaled number of cycles used per processor resource in MBB.
206 /// Critical path length. This is the number of cycles in the longest data
228 /// Minimum number of cycles from this instruction is issued to the of the
252 /// This is the number of cycles required to execute all instructions from
258 /// Return the resource length of the trace. This is the number of cycles
278 return TE.Cycles.lookup(MI);
281 /// Return the slack of MI. This is the number of cycles MI can be delaye
[all...] |
| /external/oprofile/events/i386/p6_mobile/ |
| events | 8 event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding
12 event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled
13 event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled
23 event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy
24 event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer from L2 to CPU
40 event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiving data
41 event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving BNR pin
42 event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving HIT pin
43 event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is driving HITM pin
44 event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stal
[all...] |
| /external/oprofile/events/i386/pii/ |
| events | 8 event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding
12 event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled
13 event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled
23 event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy
24 event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer from L2 to CPU
40 event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiving data
41 event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving BNR pin
42 event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving HIT pin
43 event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is driving HITM pin
44 event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stal
[all...] |
| /external/oprofile/events/i386/piii/ |
| events | 8 event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding
12 event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled
13 event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled
23 event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy
24 event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer from L2 to CPU
40 event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiving data
41 event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving BNR pin
42 event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving HIT pin
43 event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is driving HITM pin
44 event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stal
[all...] |
| /external/oprofile/events/i386/westmere/ |
| events | 11 event:0x04 counters:0,1,2,3 um:x07 minimum:200000 name:SB_DRAIN : All Store buffer stall cycles
23 event:0x14 counters:0,1,2,3 um:arith minimum:2000000 name:ARITH : Cycles the divider is busy
27 event:0x1e counters:0,1,2,3 um:x01 minimum:2000000 name:INST_QUEUE_WRITE_CYCLES : Cycles instructions are written to the instruction queue
34 event:0x3c counters:0,1,2,3 um:cpu_clk_unhalted minimum:100000 name:CPU_CLK_UNHALTED : Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
38 event:0x4f counters:0,1,2,3 um:x10 minimum:2000000 name:EPT : Extended Page Table walk cycles
42 event:0x63 counters:0,1 um:cache_lock_cycles minimum:2000000 name:CACHE_LOCK_CYCLES : Cycles L1D locked
44 event:0x80 counters:0,1,2,3 um:l1i minimum:2000000 name:L1I : L1I instruction fetch stall cycles
47 event:0x87 counters:0,1,2,3 um:ild_stall minimum:2000000 name:ILD_STALL : Any Instruction Length Decoder stall cycles
50 event:0xa2 counters:0,1,2,3 um:resource_stalls minimum:2000000 name:RESOURCE_STALLS : Resource related stall cycles
53 event:0xa8 counters:0,1,2,3 um:x01 minimum:2000000 name:LSD : Cycles when uops were delivered by the LS
[all...] |
| /frameworks/base/tests/ActivityTests/res/interpolator/ |
| slow_enter.xml | 22 android:cycles="10" />
|
| /external/llvm/lib/CodeGen/ |
| OptimizePHIs.cpp | 26 STATISTIC(NumPHICycles, "Number of PHI cycles replaced");
27 STATISTIC(NumDeadPHICycles, "Number of dead PHI cycles");
67 // Find dead PHI cycles and PHI cycles that can be replaced by a single
152 /// OptimizeBB - Remove dead PHI cycles and PHI cycles that can be replaced by
162 // Check for single-value PHI cycles.
178 // Check for dead PHI cycles.
|
| /external/oprofile/events/mips/vr5432/ |
| events | 4 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock)
|
| /external/oprofile/events/arm/armv7/ |
| events | 10 event:0x45 counters:1,2,3,4 um:zero minimum:500 name:AXI_READ_CYCLES : Number of cycles for an active AXI read
11 event:0x46 counters:1,2,3,4 um:zero minimum:500 name:AXI_WRITE_CYCLES : Number of cycles for an active AXI write
27 event:0x56 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_INST_STALL : Cycles where no instruction available
29 event:0x58 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_NEON_DATA_STALL : Number of cycles the processor waits on MRC data from NEON
30 event:0x59 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_NEON_INST_STALL : Number of cycles the processor waits on NEON instruction queue or NEON load queue
31 event:0x5A counters:1,2,3,4 um:zero minimum:500 name:NEON_CYCLES : Number of cycles NEON and integer processors are not idle
|
| events.h | 39 "Number of CPU cycles"},
52 "Number of cycles for an active AXI read"},
54 "Number of cycles for an active AXI write"},
86 "Cycles where no instruction available"},
90 "Number of cycles the processor waits on MRC data from NEON"},
92 "Number of cycles the processor waits on NEON instruction queue or NEON load queue"},
94 "Number of cycles NEON and integer processors are not idle"},
|
| /external/oprofile/events/ppc64/power7/ |
| events | 15 event:0X001 counters:0 um:zero minimum:10000 name:CYCLES : Processor Cycles
18 event:0X002 counters:3 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling
22 event:0X0010 counters:0 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor Cycles
23 event:0X0011 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
27 event:0X0015 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
35 event:0X0025 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP2 : (Group 2 pm_branch1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
43 event:0X0035 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP3 : (Group 3 pm_branch2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
51 event:0X0045 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP4 : (Group 4 pm_branch3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
59 event:0X0055 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP5 : (Group 5 pm_branch4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing usefu (…)
[all...] |
| /external/oprofile/events/i386/atom/ |
| events | 5 event:0x3c counters:0,1 um:cpu_clk_unhalted minimum:6000 name:CPU_CLK_UNHALTED : Clock cycles when not halted
6 event:0x3c counters:0,1 um:one minimum:6000 name:UNHALTED_REFERENCE_CYCLES : Unhalted reference cycles
22 event:0x14 counters:0,1 um:one minimum:6000 name:CYCLES_DIV_BUSY : Cycles the driver is busy
23 event:0x21 counters:0,1 um:core minimum:6000 name:CORE : Cycles L2 address bus is in use
24 event:0x22 counters:0,1 um:core minimum:6000 name:L2_DBUS_BUSY : Cycles the L2 cache data bus is busy
35 event:0x32 counters:0,1 um:core minimum:6000 name:L2_NO_REQ : Cycles no L2 cache requests are pending
41 event:0x62 counters:0,1 um:agent minimum:6000 name:BUS_DRDY_CLOCKS : Bus cycles when data is sent on the bus
42 event:0x63 counters:0,1 um:core,agent minimum:6000 name:BUS_LOCK_CLOCKS : Bus cycles when a LOCK signal is asserted.
43 event:0x64 counters:0,1 um:core minimum:6000 name:BUS_DATA_RCV : Bus cycles while processor receives data
70 event:0xC6 counters:0,1 um:cycles_int_masked minimum:6000 name:CYCLES_INT_MASKED : Cycles during which interrupts are disable
[all...] |
| unit_masks | 20 0x03 cycles Duration of page-walks in core cycles
36 0x00 core_p Core cycles when core is not halted
37 0x01 bus Bus cycles when core is not halted
38 0x02 no_other Bus cycles when core is active and the other is halted
82 0x01 cycles_int_masked Cycles during which interrupts are disabled
83 0x02 cycles_int_pending_and_masked Cycles during which interrupts are pending and disabled
|
| /external/webrtc/src/modules/audio_coding/codecs/isac/fix/source/ |
| fft.c | 92 /* Complexity is: 10 cycles */
149 (WebRtc_Word16)WEBRTC_SPL_MUL_16_16_RSFT(sss1Q14, bkpQx, 14); // 6 non-mul + 2 mul cycles, i.e. 8 cycles (6+2*7=20 cycles if 16x32mul)
160 //This mul segment needs 6*8 = 48 cycles for 16x16 muls, but 6*20 = 120 cycles for 16x32 muls
164 /* Complexity is: 51+48 = 99 cycles for 16x16 muls, but 51+120 = 171 cycles for 16x32 muls*/
197 /* Complexity : (31+6)*20 = 740 cycles for 16x16 muls, but (31+18)*20 = 980 cycles for 16x32 muls*
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSchedule.td | 82 int LoadLatency = -1; // Cycles for loads to access the cache.
83 int HighLatency = -1; // Approximation of cycles for "high latency" ops.
84 int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.
109 // Buffered resources may be held for multiple clock cycles, but the
213 // Optionally, ResourceCycles indicates the number of cycles the
249 class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> {
250 int Cycles = cycles;
259 // to reduce latency of a prior write by N cycles. A negative advance
265 // indicate operands that are always read this number of Cycles late
[all...] |
| /external/oprofile/events/ppc/e300/ |
| events | 3 event:0x1 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK : Cycles
14 event:0x12 counters:0,1,2,3 um:zero minimum:500 name:DECODE_STALLED : Cycles the instruction buffer was not empty, but 0 instructions decoded
15 event:0x13 counters:0,1,2,3 um:zero minimum:500 name:ISSUE_STALLED : Cycles the issue buffer is not empty but 0 instructions issued
35 event:0x64 counters:0,1,2,3 um:zero minimum:500 name:STALLS_COM_BUFFER : Cycles issue stalled due to full completion buffer
36 event:0x68 counters:0,1,2,3 um:zero minimum:500 name:STALLED_COMPLETION : Cycles that completion is stalled
37 event:0x69 counters:0,1,2,3 um:zero minimum:500 name:STALLED_LOAD : Cycles that completion is stalled due to load
38 event:0x6a counters:0,1,2,3 um:zero minimum:500 name:STALLED_FLOAT : Cycles that completion is stalled due to fp instruction
|
| /sdk/emulator/qtools/ |
| bbprof.cpp | 11 uint32_t *cycles; // number of cycles for each insn member in struct:MyStaticRec
12 uint32_t elapsed; // number of cycles for basic block
85 blocks[ii].cycles = new uint32_t[num_insns];
86 memset(blocks[ii].cycles, 0, num_insns * sizeof(uint32_t));
124 cycle_ptr = &bptr->cycles[ii];
146 uint32_t elapsed = sorted[ii]->cycles[jj];
|
| /external/oprofile/events/i386/nehalem/ |
| unit_masks | 12 0x01 cycles Counts the cycles of store buffer drains
31 0x01 reset Counts memory disambiguration reset cycles
34 0x08 watch_cycles Counts the cycles that the memory disambiguration watchdog is active
42 0x01 stalled_cycles Counts the number of cycles no Uops issued by the Register Allocation Table to the Reservation Station, i
72 0x01 cycles_div_busy Counts the number of cycles the divider is busy executing divide or square root operations
78 0x02 cycles_masked Number of cycles interrupt are masked
79 0x04 cycles_pending_and_masked Number of cycles interrupts are pending and masked
130 0x00 thread_p Counts the number of thread cycles while the thread is not in a halt state
153 # 0x02 load_buffers_full Counts cycles of L1 data cache load fill buffers ful
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/llvmpipe/ |
| lp_test_conv.c | 66 double cycles,
71 fprintf(fp, "%.1f\t", cycles / MAX2(src_type.length, dst_type.length));
163 int64_t cycles[LP_TEST_NUM_SAMPLES]; local
246 cycles[i] = end_counter - start_counter;
299 sum += cycles[i];
300 sum2 += cycles[i]*cycles[i];
309 if(fabs(cycles[i] - avg) <= 4.0*std) {
310 sum += cycles[i];
|
