| /art/compiler/sea_ir/debug/ |
| dot_gen.h | 45 // Saves the ssa def->use edges corresponding to @instruction.
46 void ToDotSSAEdges(InstructionNode* instruction);
47 void ToDotSSAEdges(PhiInstructionNode* instruction);
57 void Visit(InstructionNode* instruction);
59 void Visit(UnnamedConstInstructionNode* instruction);
61 void Visit(ConstInstructionNode* instruction) {
62 Visit(reinterpret_cast<InstructionNode*>(instruction));
64 void Visit(ReturnInstructionNode* instruction) {
65 Visit(reinterpret_cast<InstructionNode*>(instruction));
67 void Visit(IfNeInstructionNode* instruction) {
[all...] |
| /dalvik/dx/tests/032-bb-live-code/ |
| info.txt | 3 to. There is at least one example of each instruction which allows
4 flow to the subsequent instruction, and all forks of each conditional
|
| /dalvik/dx/tests/112-dex-return-jsr-result/ |
| info.txt | 5 goto instruction to be interposed between an invoke instruction and
|
| /external/llvm/test/MC/Disassembler/SystemZ/ |
| trunc-01.txt | 2 # Every instruction must be at least two bytes long.
3 # CHECK: warning: invalid instruction encoding
|
| trunc-02.txt | 2 # If the top bits are 0b10, the instruction must be 4 bytes long.
3 # CHECK: warning: invalid instruction encoding
|
| /external/llvm/test/MC/Disassembler/X86/ |
| invalid-VEX-vvvv.txt | 1 # RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 2>&1 | grep "invalid instruction encoding"
3 # This instruction would decode as movmskps if the vvvv field in the VEX prefix was all 1s.
|
| invalid-cmp-imm.txt | 1 # RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 2>&1 | grep "invalid instruction encoding"
3 # This instruction would decode as cmpordps if the immediate byte was less than 8.
5 # This instruction would decode as cmpordpd if the immediate byte was less than 8.
7 # This instruction would decode as cmpordss if the immediate byte was less than 8.
9 # This instruction would decode as cmpordsd if the immediate byte was less than 8.
|
| /external/clang/test/CodeGenObjC/ |
| arc-captured-block-var-inlined-layout.m | 20 // CHECK: Inline instruction for block variable layout: 0x0100
21 // CHECK-i386: Inline instruction for block variable layout: 0x0100
26 // CHECK: Inline instruction for block variable layout: 0x0210
27 // CHECK-i386: Inline instruction for block variable layout: 0x0210
34 // CHECK: Inline instruction for block variable layout: 0x0230
35 // CHECK-i386: Inline instruction for block variable layout: 0x0230
44 // CHECK: Inline instruction for block variable layout: 0x0231
45 // CHECK-i386: Inline instruction for block variable layout: 0x0231
56 // CHECK: Inline instruction for block variable layout: 0x0235
57 // CHECK-i386: Inline instruction for block variable layout: 0x023
[all...] |
| /art/compiler/dex/quick/arm/ |
| fp_arm.cc | 23 void ArmMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
33 case Instruction::ADD_FLOAT_2ADDR:
34 case Instruction::ADD_FLOAT:
37 case Instruction::SUB_FLOAT_2ADDR:
38 case Instruction::SUB_FLOAT:
41 case Instruction::DIV_FLOAT_2ADDR:
42 case Instruction::DIV_FLOAT:
45 case Instruction::MUL_FLOAT_2ADDR:
46 case Instruction::MUL_FLOAT:
49 case Instruction::REM_FLOAT_2ADDR
[all...] |
| /external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/Format/ |
| InstructionMethodItem.java | 44 public class InstructionMethodItem<T extends Instruction> extends MethodItem {
46 protected final T instruction; field in class:InstructionMethodItem
48 public InstructionMethodItem(CodeItem codeItem, int codeAddress, T instruction) {
51 this.instruction = instruction;
61 switch (instruction.getFormat()) {
68 if (instruction instanceof UnknownInstruction) {
70 writer.printUnsignedLongAsHex(((UnknownInstruction) instruction).getOriginalOpcode() & 0xFFFF);
238 writer.write(instruction.opcode.name);
252 writeRegister(writer, ((SingleRegisterInstruction)instruction).getRegisterA())
264 FiveRegisterInstruction instruction = (FiveRegisterInstruction)this.instruction; local
309 RegisterRangeInstruction instruction = (RegisterRangeInstruction)this.instruction; local
[all...] |
| InstructionMethodItemFactory.java | 33 import org.jf.dexlib.Code.Instruction;
42 MethodDefinition methodDefinition, CodeItem codeItem, int codeAddress, Instruction instruction) {
43 if (instruction instanceof OffsetInstruction) {
45 codeAddress, (OffsetInstruction)instruction);
48 switch (instruction.getFormat()) {
51 (ArrayDataPseudoInstruction)instruction);
54 (PackedSwitchDataPseudoInstruction)instruction);
57 (SparseSwitchDataPseudoInstruction)instruction);
60 (UnresolvedOdexInstruction)instruction);
[all...] |
| /art/compiler/sea_ir/types/ |
| type_inference_visitor.h | 27 // The TypeInferenceVisitor visits each instruction and computes its type taking into account
46 void Visit(PhiInstructionNode* instruction);
48 void Visit(InstructionNode* instruction) { }
49 void Visit(UnnamedConstInstructionNode* instruction);
50 void Visit(ConstInstructionNode* instruction) { }
51 void Visit(ReturnInstructionNode* instruction) { }
52 void Visit(IfNeInstructionNode* instruction) { }
53 void Visit(MoveResultInstructionNode* instruction);
54 void Visit(InvokeStaticInstructionNode* instruction);
55 void Visit(AddIntInstructionNode* instruction);
[all...] |
| /external/llvm/test/Analysis/CostModel/ARM/ |
| gep.ll | 8 ; folded into the instruction addressing mode.
9 ;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i8*
11 ;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i16*
13 ;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i32*
16 ;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds i64*
21 ;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds float*
23 ;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds double*
28 ;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i8>*
30 ;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i16>*
32 ;CHECK: cost of 1 for instruction: {{.*}} getelementptr inbounds <4 x i32>
[all...] |
| /external/llvm/test/Analysis/CostModel/X86/ |
| gep.ll | 9 ; the instruction addressing mode.
10 ;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i8*
12 ;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i16*
14 ;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i32*
16 ;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds i64*
19 ;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds float*
21 ;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds double*
25 ;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i8>*
27 ;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i16>*
29 ;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds <4 x i32>
[all...] |
| /external/chromium_org/sandbox/linux/seccomp-bpf/ |
| codegen.h | 13 #include "sandbox/linux/seccomp-bpf/instruction.h"
18 typedef std::vector<Instruction*> Instructions;
20 typedef std::map<const Instruction*, int> BranchTargets;
21 typedef std::map<const Instruction*, BasicBlock*> TargetsToBlocks;
27 // the limit of 255 instructions imposed by the instruction set.
37 // Instruction *dag, *branch;
64 // Create a new instruction. Instructions form a DAG. The instruction objects
68 Instruction* MakeInstruction(uint16_t code,
70 Instruction* next = NULL)
[all...] |
| /art/runtime/ |
| dex_instruction-inl.h | 27 inline int8_t Instruction::VRegA_10t() const {
32 inline uint8_t Instruction::VRegA_10x() const {
37 inline uint4_t Instruction::VRegA_11n() const {
42 inline uint8_t Instruction::VRegA_11x() const {
47 inline uint4_t Instruction::VRegA_12x() const {
52 inline int16_t Instruction::VRegA_20t() const {
57 inline uint8_t Instruction::VRegA_21c() const {
62 inline uint8_t Instruction::VRegA_21h() const {
67 inline uint8_t Instruction::VRegA_21s() const {
72 inline uint8_t Instruction::VRegA_21t() const
[all...] |
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 12 // to approximate the cost of any IR instruction when lowered to machine
43 /// Returns the expected cost of the instruction.
47 unsigned getInstructionCost(const Instruction *I) const;
108 unsigned CostModelAnalysis::getInstructionCost(const Instruction *I) const {
113 case Instruction::GetElementPtr:{
118 case Instruction::Ret:
119 case Instruction::PHI:
120 case Instruction::Br: {
123 case Instruction::Add:
124 case Instruction::FAdd
[all...] |
| /external/llvm/lib/Transforms/ObjCARC/ |
| ObjCARCUtil.cpp | 80 llvm_unreachable("Unknown instruction class!");
168 if (const Instruction *I = dyn_cast<Instruction>(V)) {
169 // Any instruction other than bitcast and gep with a pointer operand have a
176 case Instruction::Call: {
208 case Instruction::Invoke:
210 case Instruction::BitCast:
211 case Instruction::GetElementPtr:
212 case Instruction::Select: case Instruction::PHI
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.h | 45 virtual bool insnCanLoad(const Instruction *insn, int s,
46 const Instruction *ld) const;
49 virtual bool isModSupported(const Instruction *, int s, Modifier) const;
50 virtual bool isSatSupported(const Instruction *) const;
52 virtual bool mayPredicate(const Instruction *, const Value *) const;
54 virtual bool canDualIssue(const Instruction *, const Instruction *) const;
55 virtual int getLatency(const Instruction *) const;
56 virtual int getThroughput(const Instruction *) const;
|
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.h | 45 virtual bool insnCanLoad(const Instruction *insn, int s,
46 const Instruction *ld) const;
49 virtual bool isModSupported(const Instruction *, int s, Modifier) const;
50 virtual bool isSatSupported(const Instruction *) const;
52 virtual bool mayPredicate(const Instruction *, const Value *) const;
54 virtual bool canDualIssue(const Instruction *, const Instruction *) const;
55 virtual int getLatency(const Instruction *) const;
56 virtual int getThroughput(const Instruction *) const;
|
| /external/proguard/src/proguard/classfile/editor/ |
| InstructionAdder.java | 25 import proguard.classfile.instruction.visitor.InstructionVisitor;
26 import proguard.classfile.instruction.*;
58 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction)
60 // Add the instruction.
61 codeAttributeComposer.appendInstruction(offset, instruction);
67 // Create a copy of the instruction.
68 Instruction newConstantInstruction =
73 // Add the instruction.
|
| /external/proguard/src/proguard/classfile/instruction/ |
| SwitchInstruction.java | 21 package proguard.classfile.instruction;
24 * This Instruction represents a simple instruction without variable arguments
29 public abstract class SwitchInstruction extends Instruction
55 * Copies the given instruction into this instruction.
56 * @param switchInstruction the instruction to be copied.
57 * @return this instruction.
69 // Implementations for Instruction.
|
| /external/llvm/test/TableGen/ |
| DefmInsideMultiClass.td | 3 class Instruction<bits<4> opc, string Name> {
9 def rr : Instruction<opc, "rr">;
10 def rm : Instruction<opc, "rm">;
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineWorklist.h | 16 #include "llvm/IR/Instruction.h"
26 SmallVector<Instruction*, 256> Worklist;
27 DenseMap<Instruction*, unsigned> WorklistMap;
36 /// Add - Add the specified instruction to the worklist if it isn't already
38 void Add(Instruction *I) {
46 if (Instruction *I = dyn_cast<Instruction>(V))
53 void AddInitialGroup(Instruction *const *List, unsigned NumEntries) {
59 Instruction *I = List[NumEntries-1];
66 void Remove(Instruction *I)
[all...] |
| /external/proguard/src/proguard/optimize/peephole/ |
| InstructionSequencesReplacer.java | 25 import proguard.classfile.instruction.Instruction;
26 import proguard.classfile.instruction.visitor.*;
29 * This InstructionVisitor replaces multiple instruction sequences at once.
45 * instruction.
46 * @param instructionSequences the instruction sequences to be replaced,
49 * and the instruction index in the sequence.
57 Instruction[][][] instructionSequences,
72 * instruction.
73 * @param instructionSequences the instruction sequences to be replaced
[all...] |
