| /external/smali/dexlib/src/main/java/org/jf/dexlib/Code/Format/ |
| Instruction23x.java | 31 import org.jf.dexlib.Code.Instruction;
37 public class Instruction23x extends Instruction implements ThreeRegisterInstruction {
38 public static final Instruction.InstructionFactory Factory = new Factory();
88 private static class Factory implements Instruction.InstructionFactory {
89 public Instruction makeInstruction(DexFile dexFile, Opcode opcode, byte[] buffer, int bufferIndex) {
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| Instruction31i.java | 31 import org.jf.dexlib.Code.Instruction;
39 public class Instruction31i extends Instruction implements SingleRegisterInstruction, LiteralInstruction {
40 public static final Instruction.InstructionFactory Factory = new Factory();
80 private static class Factory implements Instruction.InstructionFactory {
81 public Instruction makeInstruction(DexFile dexFile, Opcode opcode, byte[] buffer, int bufferIndex) {
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| Instruction32x.java | 31 import org.jf.dexlib.Code.Instruction;
38 public class Instruction32x extends Instruction implements TwoRegisterInstruction {
39 public static final Instruction.InstructionFactory Factory = new Factory();
81 private static class Factory implements Instruction.InstructionFactory {
82 public Instruction makeInstruction(DexFile dexFile, Opcode opcode, byte[] buffer, int bufferIndex) {
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| Instruction35ms.java | 32 import org.jf.dexlib.Code.Instruction;
40 public class Instruction35ms extends Instruction implements FiveRegisterInstruction, OdexedInvokeVirtual {
41 public static final Instruction.InstructionFactory Factory = new Factory();
130 private static class Factory implements Instruction.InstructionFactory {
131 public Instruction makeInstruction(DexFile dexFile, Opcode opcode, byte[] buffer, int bufferIndex) {
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| Instruction3rms.java | 31 import org.jf.dexlib.Code.Instruction;
39 public class Instruction3rms extends Instruction implements RegisterRangeInstruction, OdexedInvokeVirtual {
40 public static final Instruction.InstructionFactory Factory = new Factory();
102 private static class Factory implements Instruction.InstructionFactory {
103 public Instruction makeInstruction(DexFile dexFile, Opcode opcode, byte[] buffer, int bufferIndex) {
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| Instruction51l.java | 31 import org.jf.dexlib.Code.Instruction;
39 public class Instruction51l extends Instruction implements SingleRegisterInstruction, LiteralInstruction {
40 public static final Instruction.InstructionFactory Factory = new Factory();
80 private static class Factory implements Instruction.InstructionFactory {
81 public Instruction makeInstruction(DexFile dexFile, Opcode opcode, byte[] buffer, int bufferIndex) {
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| /external/chromium_org/v8/src/mips/ |
| constants-mips.h | 40 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n")
77 // Volume II: The MIPS32 Instruction Set
236 // Instruction bit masks.
254 // MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set.
600 // A nop instruction. (Encoding of sll 0 0 0).
603 class Instruction {
609 // always the value of the current instruction being executed.
613 // Get the raw instruction bits.
618 // Set the raw instruction bits to value.
623 // Read one particular bit out of the instruction bits
[all...] |
| /external/v8/src/mips/ |
| constants-mips.h | 40 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n")
76 // Volume II: The MIPS32 Instruction Set
233 // Instruction bit masks.
251 // MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set.
589 // A nop instruction. (Encoding of sll 0 0 0).
592 class Instruction {
598 // always the value of the current instruction being executed.
602 // Get the raw instruction bits.
607 // Set the raw instruction bits to value.
612 // Read one particular bit out of the instruction bits
[all...] |
| /dalvik/dx/src/com/android/dx/cf/direct/ |
| CodeObserver.java | 197 * Helper to produce the first bit of output for each instruction.
199 * @param offset the offset to the start of the instruction
222 * @param offset offset to the instruction
223 * @param length instruction length
249 * @param offset offset to the instruction
250 * @param length instruction length
273 * @param offset offset to the instruction
274 * @param length instruction length
291 * @param offset offset to the instruction
292 * @param length instruction lengt
[all...] |
| /dalvik/vm/analysis/ |
| CodeVerify.h | 127 * instruction. We track the status of all registers, and (if the method
146 * address of the new-instance instruction. One per method.
174 * Number of registers we track for each instruction. This is equal
181 * Instruction widths and flags, one entry per code unit.
194 * instruction. For register map generation, we're only interested
219 * of an instruction.
226 * Extract the unsigned 16-bit instruction width from "flags".
283 * Instruction is a branch target or exception handler?
299 * Instruction is a GC point?
328 * instruction widths and "in try" flags
[all...] |
| /external/llvm/include/llvm/Transforms/Utils/ |
| SSAUpdater.h | 22 class Instruction;
137 LoadAndStorePromoter(const SmallVectorImpl<Instruction*> &Insts,
146 void run(const SmallVectorImpl<Instruction*> &Insts) const;
149 /// \brief Return true if the specified instruction is in the Inst list.
153 virtual bool isInstInList(Instruction *I,
154 const SmallVectorImpl<Instruction*> &Insts) const;
166 /// \brief Called before each instruction is deleted.
167 virtual void instructionDeleted(Instruction *I) const {
170 /// \brief Called to update debug info associated with the instruction.
171 virtual void updateDebugInfo(Instruction *I) const
[all...] |
| /external/oprofile/events/arm/armv7/ |
| events.h | 5 "Instruction fetch misses from cache or normal cacheable memory"},
7 "Instruction fetch misses from TLB"},
25 "Instruction that writes to the Context ID Register architecturally executed"},
29 "Immediate branch instruction executed (taken or not)"},
62 "L1 instruction cache miss as a result of the hashing algorithm"},
74 "Any L1 instruction cache access, excluding CP15 cache accesses"},
84 "Number of operations executed (in instruction or mutli-cycle instruction)"},
86 "Cycles where no instruction available"},
92 "Number of cycles the processor waits on NEON instruction queue or NEON load queue"}
[all...] |
| /external/oprofile/events/mips/24K/ |
| events.h | 15 "5-0 Instruction micro-TLB accesses"},
19 "7-0 Joint TLB instruction accesses"},
21 "8-0 Joint TLB data (non-instruction) accesses"},
23 "9-0 Instruction cache accesses"},
63 "37-0 Stall cycles due to an instruction cache miss"},
85 "49-0 EJTAG instruction triggerpoints"},
105 "5-1 Instruction micro-TLB misses"},
109 "7-1 Joint TLB instruction misses"},
111 "8-1 Joint TLB data (non-instruction) misses"},
113 "9-1 Instruction cache misses"}
[all...] |
| /external/proguard/src/proguard/optimize/ |
| TailRecursionSimplifier.java | 29 import proguard.classfile.instruction.*;
30 import proguard.classfile.instruction.visitor.InstructionVisitor;
145 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction)
147 // Copy the instruction.
148 codeAttributeComposer.appendInstruction(offset, instruction.shrink());
166 // Is the next instruction a return?
170 Instruction nextInstruction =
203 // The original return instruction will be
225 // Copy the instruction
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 12 // "Fast" instruction selection is designed to emit very poor code quickly.
20 // "Fast" instruction selection is able to fail gracefully and transfer
25 // The intended use for "fast" instruction selection is "-O0" mode
30 // time. Despite its limitations, "fast" instruction selection is able to
35 // the same instruction descriptions that the SelectionDAG selector reads,
80 // contains labels or copies, use the last instruction as the last local
115 const Instruction *I = dyn_cast<Instruction>(V);
133 !(I->getOpcode() == Instruction::BitCast ||
134 I->getOpcode() == Instruction::PtrToInt |
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_peephole.cpp | 34 Instruction::isNop() const
62 bool Instruction::isDead() const
95 Instruction *mov, *si, *next;
122 void checkSwapSrc01(Instruction *);
124 bool isCSpaceLoad(Instruction *);
125 bool isImmd32Load(Instruction *);
126 bool isAttribOrSharedLoad(Instruction *);
130 LoadPropagation::isCSpaceLoad(Instruction *ld)
136 LoadPropagation::isImmd32Load(Instruction *ld)
144 LoadPropagation::isAttribOrSharedLoad(Instruction *ld
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_peephole.cpp | 34 Instruction::isNop() const
62 bool Instruction::isDead() const
95 Instruction *mov, *si, *next;
122 void checkSwapSrc01(Instruction *);
124 bool isCSpaceLoad(Instruction *);
125 bool isImmd32Load(Instruction *);
126 bool isAttribOrSharedLoad(Instruction *);
130 LoadPropagation::isCSpaceLoad(Instruction *ld)
136 LoadPropagation::isImmd32Load(Instruction *ld)
144 LoadPropagation::isAttribOrSharedLoad(Instruction *ld
[all...] |
| /external/llvm/lib/IR/ |
| Constants.cpp | 260 case Instruction::UDiv:
261 case Instruction::SDiv:
262 case Instruction::FDiv:
263 case Instruction::URem:
264 case Instruction::SRem:
265 case Instruction::FRem:
352 if (CE->getOpcode() == Instruction::Sub) {
356 LHS->getOpcode() == Instruction::PtrToInt &&
357 RHS->getOpcode() == Instruction::PtrToInt &&
[all...] |
| /external/chromium_org/v8/src/arm/ |
| constants-arm.h | 40 // Use UDF, the permanently undefined instruction.
145 // Instruction objects are pointers to 32bit values, and provide methods to
185 // Instruction encoding bits and masks.
192 A = 1 << 21, // Accumulate in multiply instruction (or not).
219 // Instruction bit masks.
222 kRdMask = 15 << 12, // In str instruction.
234 // Addressing modes and instruction variants.
437 // add(sp, sp, 4) instruction (aka Pop())
440 // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r))
444 // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)
[all...] |
| /art/compiler/utils/arm/ |
| constants_arm.h | 163 // instructions. Based on the "Figure 3-1 ARM instruction set summary".
186 // Immediate instruction fields encoding.
192 // Shift instruction register fields encodings.
199 // Load/store instruction offset field encoding.
204 // Mul instruction register fields encodings.
221 // architecture instruction set encoding as described in figure A3-1.
223 // Example: Test whether the instruction at ptr does set the condition code
244 // Get the raw instruction bits.
249 // Set the raw instruction bits to value.
254 // Read one particular bit out of the instruction bits
[all...] |
| /external/proguard/src/proguard/classfile/instruction/ |
| Instruction.java | 21 package proguard.classfile.instruction;
25 import proguard.classfile.instruction.visitor.InstructionVisitor;
32 public abstract class Instruction
664 * Returns the canonical opcode of this instruction, i.e. typically the
674 * Shrinks this instruction to its shortest possible form.
675 * @return this instruction.
677 public abstract Instruction shrink();
682 * Writes the Instruction at the given offset in the given code attribute.
691 * Writes the Instruction at the given offset in the given code array.
710 * Returns whether the instruction is wide, i.e. preceded by a wide opcode
[all...] |
| /frameworks/compile/slang/BitWriter_2_9_func/ |
| BitcodeWriter.cpp | 65 default: llvm_unreachable("Unknown cast instruction!");
66 case Instruction::Trunc : return bitc::CAST_TRUNC;
67 case Instruction::ZExt : return bitc::CAST_ZEXT;
68 case Instruction::SExt : return bitc::CAST_SEXT;
69 case Instruction::FPToUI : return bitc::CAST_FPTOUI;
70 case Instruction::FPToSI : return bitc::CAST_FPTOSI;
71 case Instruction::UIToFP : return bitc::CAST_UITOFP;
72 case Instruction::SIToFP : return bitc::CAST_SITOFP;
73 case Instruction::FPTrunc : return bitc::CAST_FPTRUNC;
74 case Instruction::FPExt : return bitc::CAST_FPEXT
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILPeepholeOptimizer.cpp | 53 // Function to initiate all of the instruction level optimizations.
73 // Run a series of tests to see if we can optimize a CALL instruction.
76 bool optimizeBitExtract(Instruction *inst);
78 bool optimizeBitInsert(Instruction *inst);
79 bool setupBitInsert(Instruction *base,
80 Instruction *&src,
83 // Expand the bit field insert instruction on versions of OpenCL that
86 // Expand the bit field mask instruction on version of OpenCL that
105 bool correctMisalignedMemOp(Instruction *inst);
300 Instruction *inst = (*bbb)
[all...] |
| /external/chromium_org/third_party/tcmalloc/chromium/src/windows/ |
| preamble_patcher_with_stub.cc | 105 // Note that the first byte of the trampoline is a NOP instruction. This
136 // bytes for our jmp instruction, so let's find the minimum number of
164 "instruction in the initial preamble bytes.");
189 "Disassembler encountered unsupported instruction "
210 // Now, make a jmp instruction to the rest of the target function (minus the
212 // find address to jump to, relative to next address after jmp instruction
223 // jmp (Jump near, relative, displacement relative to next instruction)
251 // (Jump near, relative, displacement relative to next instruction)
254 // Find offset from instruction after jmp, to the replacement function.
265 // complete the jmp instruction
[all...] |
| /external/chromium_org/third_party/tcmalloc/vendor/src/windows/ |
| preamble_patcher_with_stub.cc | 105 // Note that the first byte of the trampoline is a NOP instruction. This
136 // bytes for our jmp instruction, so let's find the minimum number of
164 "instruction in the initial preamble bytes.");
189 "Disassembler encountered unsupported instruction "
210 // Now, make a jmp instruction to the rest of the target function (minus the
212 // find address to jump to, relative to next address after jmp instruction
223 // jmp (Jump near, relative, displacement relative to next instruction)
251 // (Jump near, relative, displacement relative to next instruction)
254 // Find offset from instruction after jmp, to the replacement function.
265 // complete the jmp instruction
[all...] |
