| /external/llvm/test/CodeGen/X86/ |
| codegen-prepare.ll | 4 ; does not wrongly rewrite the address computed by Instruction %4
10 ; - the store instruction stores a value at address [60 + %this]
11 ; - the first load instruction loads a value at address [12 + %this]
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
| radeon_compiler_util_tests.c | 37 * CMP instruction. A previous version of this function was ignoring
57 * instruction share the same register file and index. Normally, we
60 * source selects that the presubtract instruction expects
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.h | 1 //===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
38 /// getEncodingType - Returns the encoding type of this instruction.
57 // First 4 bits are the instruction encoding
|
| /external/mesa3d/src/mesa/program/ |
| prog_instruction.h | 29 * Vertex/fragment program instruction datatypes and constants.
53 #define SWIZZLE_ZERO 4 /**< For SWZ instruction only */
54 #define SWIZZLE_ONE 5 /**< For SWZ instruction only */
109 * Instruction precision for GL_NV_fragment_program
142 * Program instruction opcodes for vertex, fragment and geometry programs.
254 * Instruction source register.
271 * instruction which allows per-component negation.
294 * Instruction destination register.
336 * Vertex/fragment program instruction.
345 * Indicates that the instruction should update the condition cod
[all...] |
| /external/oprofile/events/mips/20K/ |
| events | 15 event:0x9 counters:0 um:zero minimum:500 name:INSN_REQ_FROM_IFU_TO_BIU : Instruction requests from the IFU to the BIU
19 event:0xd counters:0 um:zero minimum:500 name:JR_INSNS_COMPLETED : JR instruction that completed execution
21 event:0xf counters:0 um:zero minimum:500 name:INSNS_COMPLETED : Instruction that completed execution (with or without exception)
|
| /external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/ |
| CatchMethodItem.java | 50 //use the address from the last covered instruction, but make the label
51 //name refer to the address of the next instruction
74 //sort after instruction and end_try label
|
| /external/smali/dexlib/src/main/java/org/jf/dexlib/Code/Format/ |
| Instruction10x.java | 31 import org.jf.dexlib.Code.Instruction;
36 public class Instruction10x extends Instruction {
60 public Instruction makeInstruction(DexFile dexFile, Opcode opcode, byte[] buffer, int bufferIndex) {
|
| /libcore/dom/src/test/java/org/w3c/domts/level1/core/ |
| nodeprocessinginstructionnodevalue.java | 32 * Processing Instruction Node is the content of the
33 * Processing Instruction(exclude the target).
35 * Retrieve the Processing Instruction node in the XML file
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/ |
| vm86.h | 45 #define VM86_UNKNOWN 1 /* unhandled GP fault - IO-instruction or similar */
46 #define VM86_INTx 2 /* int3/int x instruction (ARG = x) */
47 #define VM86_STI 3 /* sti/popf/iret instruction enabled virtual interrupts */
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
| vm86.h | 45 #define VM86_UNKNOWN 1 /* unhandled GP fault - IO-instruction or similar */
46 #define VM86_INTx 2 /* int3/int x instruction (ARG = x) */
47 #define VM86_STI 3 /* sti/popf/iret instruction enabled virtual interrupts */
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
| vm86.h | 45 #define VM86_UNKNOWN 1 /* unhandled GP fault - IO-instruction or similar */
46 #define VM86_INTx 2 /* int3/int x instruction (ARG = x) */
47 #define VM86_STI 3 /* sti/popf/iret instruction enabled virtual interrupts */
|
| /external/llvm/lib/Transforms/Utils/ |
| IntegerDivision.cpp | 29 /// instruction. This will generate a urem in the process, and Builder's insert
55 if (Instruction *URemInst = dyn_cast<Instruction>(URem))
64 /// code generated, e.g. at the urem instruction. This will generate a udiv in
78 if (Instruction *UDiv = dyn_cast<Instruction>(Quotient))
86 /// code generated, e.g. at the sdiv instruction. This will generate a udiv in
116 if (Instruction *UDiv = dyn_cast<Instruction>(Q_Mag))
124 /// the caller wants code generated, e.g. at the udiv instruction
[all...] |
| /art/compiler/dex/quick/ |
| codegen_util.cc | 58 /* Convert an instruction to a NOP */
115 /* Pretty-print a LIR instruction */
138 lir->operands[0] = reinterpret_cast<uintptr_t>("No instruction string");
317 * instruction streams.
404 * instruction that does the launch, so we have to subtract
419 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set;
424 if (tab_rec->table[0] == Instruction::kSparseSwitchSignature) {
439 static_cast<int>(Instruction::kPackedSwitchSignature));
670 if (tab_rec->table[0] == Instruction::kSparseSwitchSignature) {
674 static_cast<int>(Instruction::kPackedSwitchSignature))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 64 virtual bool TargetSelectInstruction(const Instruction *I);
67 /// vreg is being provided by the specified load instruction. If possible,
68 /// try to fold the load as an operand to the instruction, returning true if
93 bool X86SelectLoad(const Instruction *I);
95 bool X86SelectStore(const Instruction *I);
97 bool X86SelectRet(const Instruction *I);
99 bool X86SelectCmp(const Instruction *I);
101 bool X86SelectZExt(const Instruction *I);
103 bool X86SelectBranch(const Instruction *I);
105 bool X86SelectShift(const Instruction *I)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_bb.cpp | 61 delete_Instruction(prog, reinterpret_cast<Instruction *>(it.get()));
97 for (Instruction *i = getFirst(); i; i = i->next)
118 BasicBlock::insertHead(Instruction *inst)
152 BasicBlock::insertTail(Instruction *inst)
182 BasicBlock::insertBefore(Instruction *q, Instruction *p)
212 BasicBlock::insertAfter(Instruction *p, Instruction *q)
235 BasicBlock::remove(Instruction *insn)
266 void BasicBlock::permuteAdjacent(Instruction *a, Instruction *b
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineTraceMetrics.h | 41 // Every instruction in the current block has a slack - the number of cycles
42 // execution of the instruction can be delayed without extending the critical
123 /// For virtual registers: Minimum height of the defining instruction.
176 /// useful instruction depths. A dominating block can be above the current
185 // Instruction depths are only comparable if the traces share a head.
192 // increase the instruction depth.
196 // Data-dependency-related information. Per-instruction depth and height
200 /// Instruction depths have been computed. This implies hasValidDepth().
203 /// Instruction heights have been computed. This implies hasValidHeight().
220 /// InstrCycles represents the cycle height and depth of an instruction in
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
190 /// analyzeCompare - For a comparison instruction, return the source registers
192 /// compares against in CmpValue. Return true if the comparison instruction
198 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
200 /// instruction if the flags can be updated in the same way by an earlier
201 /// instruction such as SUB.
214 /// instruction, try to fold the immediate into the use instruction.
281 /// verifyInstruction - Perform target specific instruction verification.
297 /// instruction
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_bb.cpp | 61 delete_Instruction(prog, reinterpret_cast<Instruction *>(it.get()));
97 for (Instruction *i = getFirst(); i; i = i->next)
118 BasicBlock::insertHead(Instruction *inst)
152 BasicBlock::insertTail(Instruction *inst)
182 BasicBlock::insertBefore(Instruction *q, Instruction *p)
212 BasicBlock::insertAfter(Instruction *p, Instruction *q)
235 BasicBlock::remove(Instruction *insn)
266 void BasicBlock::permuteAdjacent(Instruction *a, Instruction *b
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| CodeGenPrepare.cpp | 86 /// next instruction to optimize. Xforms that can invalidate this should
124 bool OptimizeInst(Instruction *I);
125 bool OptimizeMemoryInst(Instruction *I, Value *Addr, Type *AccessTy);
128 bool MoveExtToFormExtLoad(Instruction *I);
129 bool OptimizeExtUses(Instruction *I);
283 // If the instruction before the branch (skipping debug info) isn't a phi
323 const Instruction *User = cast<Instruction>(*UI);
332 Instruction *Insn = dyn_cast<Instruction>(UPN->getIncomingValue(I))
[all...] |
| /art/runtime/ |
| dex_instruction.cc | 25 const char* const Instruction::kInstructionNames[] = {
33 Instruction::Format const Instruction::kInstructionFormats[] = {
41 int const Instruction::kInstructionFlags[] = {
49 int const Instruction::kInstructionVerifyFlags[] = {
57 int const Instruction::kInstructionSizeInCodeUnits[] = {
85 bool Instruction::HasVRegC() const {
94 bool Instruction::HasVRegB() const {
108 bool Instruction::HasVRegA() const {
132 int32_t Instruction::VRegC() const
[all...] |
| /art/runtime/verifier/ |
| register_line.h | 49 // During verification, we associate one of these with every "interesting" instruction. We track
179 const RegType& GetInvocationThis(const Instruction* inst, bool is_range)
183 * Verify types for a simple two-register instruction (e.g. "neg-int").
186 void CheckUnaryOp(const Instruction* inst, const RegType& dst_type,
190 void CheckUnaryOpWide(const Instruction* inst,
195 void CheckUnaryOpToWide(const Instruction* inst,
200 void CheckUnaryOpFromWide(const Instruction* inst,
206 * Verify types for a simple three-register instruction (e.g. "add-int").
210 void CheckBinaryOp(const Instruction* inst,
215 void CheckBinaryOpWide(const Instruction* inst
[all...] |
| /cts/tools/vm-tests-tf/src/dot/junit/opcodes/move_result/ |
| Test_move_result.java | 90 * @title move-result instruction must be immediately preceded
91 * (in the insns array) by an <invoke-kind> instruction
104 * @title move-result instruction must be immediately preceded
105 * (in actual control flow) by an <invoke-kind> instruction
|
| /cts/tools/vm-tests-tf/src/dot/junit/opcodes/move_result_object/ |
| Test_move_result_object.java | 101 * @title move-result-object instruction must be immediately preceded
102 * (in the insns array) by an <invoke-kind> instruction
115 * @title move-result-object instruction must be immediately preceded
116 * (in actual control flow) by an <invoke-kind> instruction
|
| /cts/tools/vm-tests-tf/src/dot/junit/opcodes/move_result_wide/ |
| Test_move_result_wide.java | 90 * @title move-result-wide instruction must be immediately preceded
91 * (in the insns array) by an <invoke-kind> instruction
104 * @title move-result-wide instruction must be immediately preceded
105 * (in actual control flow) by an <invoke-kind> instruction
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| Dop.java | 29 /** {@code non-null;} the instruction format */
44 * @param format {@code non-null;} the instruction format
100 * Gets the instruction format.
102 * @return {@code non-null;} the instruction format
|
