| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_info.c | 176 * Process an instruction, and update the register values accordingly.
189 for (i = 0; i < inst->Instruction.NumDstRegs; ++i) {
215 switch (inst->Instruction.Opcode) {
260 if (!inst->Instruction.Predicate &&
261 !inst->Instruction.Saturate) {
264 if (inst->Instruction.Opcode == TGSI_OPCODE_MOV) {
267 } else if (inst->Instruction.Opcode == TGSI_OPCODE_MUL) {
304 switch (inst->Instruction.Opcode) {
428 if (inst->Instruction.Opcode == TGSI_OPCODE_END ||
429 inst->Instruction.Opcode == TGSI_OPCODE_BGNSUB)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/program/ |
| prog_instruction.c | 34 * Initialize program instruction fields to defaults.
35 * \param inst first instruction to initialize
67 * \return pointer to instruction memory
83 * \param numNewInst desired size of new instruction array.
84 * \return pointer to start of new instruction array.
140 * Basic info about each instruction
151 * Instruction info
254 * Return the number of src registers for the given instruction/opcode.
267 * Return the number of dst registers for the given instruction/opcode.
300 * The second instruction will have the wrong value for t0 if executed as-is
[all...] |
| /external/llvm/lib/DebugInfo/ |
| DWARFDebugFrame.cpp | 63 /// An entry may contain CFI instructions. An instruction consists of an
66 struct Instruction {
67 Instruction(uint8_t Opcode)
75 std::vector<Instruction> Instructions;
77 /// Convenience methods to add a new instruction with the given opcode and
80 Instructions.push_back(Instruction(Opcode));
84 Instructions.push_back(Instruction(Opcode));
89 Instructions.push_back(Instruction(Opcode));
186 // TODO: at the moment only instruction names are dumped. Expand this to
188 for (std::vector<Instruction>::const_iterator I = Instructions.begin()
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 29 // This is a PPC pseudo-instruction.
54 // branch instruction per-cycle.
71 // 3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
132 /// getHazardType - We return hazard for any non-branch instruction that would
152 // We can only issue a PPC970_First/PPC970_Single instruction (such as
157 // If this instruction is cracked into two ops by the decoder, we know that
164 default: llvm_unreachable("Unknown instruction type!");
170 // We can only issue a branch as the last instruction in a group.
174 // We can only issue a CR instruction in the first two slots.
226 // If this instruction is cracked into two ops by the decoder, remember tha
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86VZeroUpper.cpp | 1 //===-- X86VZeroUpper.cpp - AVX vzeroupper instruction inserter -----------===//
44 const TargetInstrInfo *TII; // Machine instruction info.
59 // until the MBB exit there isn't a instruction using YMM to change
68 // vzeroupper instruction.
243 // We found a ymm-using instruction; this could be an AVX instruction,
256 // The VZEROUPPER instruction resets the upper 128 bits of all Intel AVX
257 // registers. This instruction has zero latency. In addition, the processor
260 // the VZEROUPPER instruction before any function call/return that might
288 // 2) There are no calls, and and a non-call instruction marks this block
[all...] |
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_info.c | 176 * Process an instruction, and update the register values accordingly.
189 for (i = 0; i < inst->Instruction.NumDstRegs; ++i) {
215 switch (inst->Instruction.Opcode) {
260 if (!inst->Instruction.Predicate &&
261 !inst->Instruction.Saturate) {
264 if (inst->Instruction.Opcode == TGSI_OPCODE_MOV) {
267 } else if (inst->Instruction.Opcode == TGSI_OPCODE_MUL) {
304 switch (inst->Instruction.Opcode) {
428 if (inst->Instruction.Opcode == TGSI_OPCODE_END ||
429 inst->Instruction.Opcode == TGSI_OPCODE_BGNSUB)
[all...] |
| /external/mesa3d/src/mesa/program/ |
| prog_instruction.c | 34 * Initialize program instruction fields to defaults.
35 * \param inst first instruction to initialize
67 * \return pointer to instruction memory
83 * \param numNewInst desired size of new instruction array.
84 * \return pointer to start of new instruction array.
140 * Basic info about each instruction
151 * Instruction info
254 * Return the number of src registers for the given instruction/opcode.
267 * Return the number of dst registers for the given instruction/opcode.
300 * The second instruction will have the wrong value for t0 if executed as-is
[all...] |
| /external/oprofile/events/mips/1004K/ |
| events.h | 15 "5-0 Instruction micro-TLB accesses"},
19 "7-0 Joint TLB instruction accesses"},
21 "8-0 Joint TLB data (non-instruction) accesses"},
23 "9-0 Instruction cache accesses"},
73 "37-0 Stall cycles due to an instruction cache miss"},
95 "49-0 EJTAG instruction triggerpoints"},
129 "5-1 Instruction micro-TLB misses"},
133 "7-1 Joint TLB instruction misses"},
135 "8-1 Joint TLB data (non-instruction) misses"},
137 "9-1 Instruction cache misses"}
[all...] |
| /external/oprofile/events/mips/34K/ |
| events.h | 15 "5-0 Instruction micro-TLB accesses"},
19 "7-0 Joint TLB instruction accesses"},
21 "8-0 Joint TLB data (non-instruction) accesses"},
23 "9-0 Instruction cache accesses"},
71 "37-0 Stall cycles due to an instruction cache miss"},
93 "49-0 EJTAG instruction triggerpoints"},
115 "5-1 Instruction micro-TLB misses"},
119 "7-1 Joint TLB instruction misses"},
121 "8-1 Joint TLB data (non-instruction) misses"},
123 "9-1 Instruction cache misses"}
[all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | 340 case Instruction::Load:
344 case Instruction::And: {
357 case Instruction::Or: {
369 case Instruction::Xor: {
382 case Instruction::Mul: {
388 case Instruction::UDiv: {
406 case Instruction::Select:
417 case Instruction::FPTrunc:
418 case Instruction::FPExt:
419 case Instruction::FPToUI
[all...] |
| /external/llvm/lib/Transforms/ObjCARC/ |
| ObjCARCOpts.cpp | 227 // Use by an instruction which copies the value is an escape if the
453 SmallPtrSet<Instruction *, 2> Calls;
457 SmallPtrSet<Instruction *, 2> ReverseInsertPts;
501 for (SmallPtrSet<Instruction *, 2>::const_iterator
602 void InsertCall(Instruction *I) {
606 void InsertReverseInsertPt(Instruction *I) {
875 /// instruction so that we can track backwards when post processing via the llvm
881 // If pointer is a result of an instruction and it does not have a source
883 // an instruction and does have a source MDNode attached to it, return a
885 if (Instruction *Inst = dyn_cast<Instruction>(Ptr))
[all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 112 int offset; // Offset of this instruction.
175 LIR* anchor; // Reference instruction for relative offsets.
279 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2);
379 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div,
392 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1,
394 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src,
397 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest,
420 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest,
422 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest,
424 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest
[all...] |
| /art/compiler/sea_ir/ir/ |
| sea.cc | 202 // This maps target instruction pointers to their corresponding region objects.
205 // Pass: Find the start instruction of basic blocks
208 const art::Instruction* inst = art::Instruction::At(&code[i]);
235 const art::Instruction* inst = art::Instruction::At(&code[i]);
467 void Region::AddChild(sea_ir::InstructionNode* instruction) {
468 DCHECK(instruction) << "Tried to add NULL instruction to region node.";
469 instructions_.push_back(instruction);
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| RopTranslator.java | 130 * objects per basic block (to the first and last instruction,
139 * extra instruction per block (for the locals state at the
252 * Choose and append an output instruction for each original
253 * instruction.
439 * given rop instruction. For insns that are commutative, have
443 * @param insn {@code non-null;} instruction in question
444 * @return {@code non-null;} the instruction's complete register list
452 * given rop instruction. For insns that are commutative, have
456 * @param insn {@code non-null;} instruction in question
458 * @return {@code non-null;} the instruction's complete register lis
[all...] |
| DalvInsn.java | 46 * Makes a move instruction, appropriate and ideal for the given arguments.
80 * <p><b>Note:</b> In the unlikely event that an instruction takes
143 * Gets whether the address of this instruction is known.
153 * Gets the output address of this instruction, if it is known. This throws
187 * Gets the register list for this instruction.
207 * Gets the minimum distinct registers required for this instruction.
229 * Gets the instruction prefix required, if any, to use in a high
253 * Gets the instruction suffix required, if any, to use in a high
270 * Gets the instruction that is equivalent to this one, except that
289 * Gets the short identifier for this instruction. This is it
[all...] |
| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/parsers/nasm/ |
| nasm-token.re | 260 parser_nasm->state = INSTRUCTION;
265 parser_nasm->state = INSTRUCTION;
270 parser_nasm->state = INSTRUCTION;
275 parser_nasm->state = INSTRUCTION;
280 parser_nasm->state = INSTRUCTION;
285 parser_nasm->state = INSTRUCTION;
290 parser_nasm->state = INSTRUCTION;
295 parser_nasm->state = INSTRUCTION;
300 parser_nasm->state = INSTRUCTION;
306 parser_nasm->state = INSTRUCTION;
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| RopTranslator.java | 136 * objects per basic block (to the first and last instruction,
145 * extra instruction per block (for the locals state at the
259 * Choose and append an output instruction for each original
260 * instruction.
446 * given rop instruction. For insns that are commutative, have
450 * @param insn {@code non-null;} instruction in question
451 * @return {@code non-null;} the instruction's complete register list
459 * given rop instruction. For insns that are commutative, have
463 * @param insn {@code non-null;} instruction in question
465 * @return {@code non-null;} the instruction's complete register lis
[all...] |
| /external/llvm/lib/IR/ |
| ConstantsContext.h | 81 : ConstantExpr(C2->getType(), Instruction::Select, &Op<0>(), 3) {
103 Instruction::ExtractElement, &Op<0>(), 2) {
123 : ConstantExpr(C1->getType(), Instruction::InsertElement,
148 Instruction::ShuffleVector,
172 : ConstantExpr(DestTy, Instruction::ExtractValue, &Op<0>(), 1),
198 : ConstantExpr(DestTy, Instruction::InsertValue, &Op<0>(), 2),
244 CompareConstantExpr(Type *ty, Instruction::OtherOps opc,
437 if (Instruction::isCast(V.opcode))
439 if ((V.opcode >= Instruction::BinaryOpsBegin &&
440 V.opcode < Instruction::BinaryOpsEnd)
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 175 /// @param isBranch - If the instruction is a branch instruction
176 /// @param Address - The starting address of the instruction
177 /// @param Offset - The byte offset to this immediate in the instruction
178 /// @param Width - The byte width of this immediate in the instruction
182 /// immediate in the instruction using the Address, Offset and Width. If that
198 /// referenced by a load instruction with the base register that is the rip.
200 /// instruction and its immediate Value are used to determine the address
215 /// @param insn - The internal instruction.
328 /// @param insn - The internal instruction to extract the R/M fiel
[all...] |
| /dalvik/vm/compiler/codegen/arm/ |
| LocalOptimizations.cpp | 54 /* Convert a more expensive instruction (ie load) into a move */
62 * Insert the converted instruction after the original since the
63 * optimization is scannng in the top-down order and the new instruction
71 * Perform a pass of top-down walk, from the second-last instruction in the
121 * Add r15 (pc) to the resource mask to prevent this instruction
153 * Should only see literal loads in the instruction
252 * since the instruction list is scanned in the
268 * Perform a pass of bottom-up walk, from the second instruction in the
285 /* Start from the second instruction */
358 * Store the dependent or non-pseudo/indepedent instruction to th
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| LocalOptimizations.cpp | 54 /* Convert a more expensive instruction (ie load) into a move */
62 * Insert the converted instruction after the original since the
63 * optimization is scannng in the top-down order and the new instruction
71 * Perform a pass of top-down walk, from the second-last instruction in the
121 * Add r15 (pc) to the resource mask to prevent this instruction
153 * Should only see literal loads in the instruction
252 * since the instruction list is scanned in the
268 * Perform a pass of bottom-up walk, from the second instruction in the
285 /* Start from the second instruction */
358 * Store the dependent or non-pseudo/indepedent instruction to th
[all...] |
| /dalvik/vm/mterp/out/ |
| InterpAsm-mips.S | 29 s3 rIBASE interpreted instruction base pointer, used for computed goto
30 s4 rINST first 16-bit code unit of current instruction
114 * Put the prefetched instruction's opcode field into the specified register.
460 beq a3, a4, 1f # don't profile the next instruction?
465 GOTO_OPCODE(t0) # jump to next instruction
467 /* start executing the instruction at rPC */
470 GOTO_OPCODE(t0) # jump to next instruction
576 GOTO_OPCODE(t0) # jump to next instruction
593 GOTO_OPCODE(t0) # jump to next instruction
610 GOTO_OPCODE(t0) # jump to next instruction
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/ |
| tgsi_sanity.c | 317 if (inst->Instruction.Opcode == TGSI_OPCODE_END) {
324 info = tgsi_get_opcode_info( inst->Instruction.Opcode );
326 report_error( ctx, "(%u): Invalid instruction opcode", inst->Instruction.Opcode );
330 if (info->num_dst != inst->Instruction.NumDstRegs) {
333 if (info->num_src != inst->Instruction.NumSrcRegs) {
340 for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
351 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
399 /* No declarations allowed after the first instruction.
402 report_error( ctx, "Instruction expected but declaration found" )
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/util/ |
| u_pstipple.c | 248 * TGSI instruction transform callback.
249 * Before the first instruction, insert our new code to sample the
268 /* emit our new declarations before the first instruction */
358 newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
359 newInst.Instruction.NumDstRegs = 1;
362 newInst.Instruction.NumSrcRegs = 2;
371 newInst.Instruction.Opcode = TGSI_OPCODE_TEX;
372 newInst.Instruction.NumDstRegs = 1;
375 newInst.Instruction.NumSrcRegs = 2;
376 newInst.Instruction.Texture = TRUE
[all...] |
| /external/chromium_org/v8/src/ |
| lithium-allocator.h | 63 // For each lithium instruction there are exactly two lifetime positions:
64 // the beginning and the end of the instruction. Lifetime positions for
69 // the instruction with the given index.
79 // Returns the index of the instruction to which this lifetime position
86 // Returns true if this lifetime position corresponds to the instruction
92 // Returns the lifetime position for the start of the instruction which
99 // Returns the lifetime position for the end of the instruction which
106 // Returns the lifetime position for the beginning of the next instruction.
113 // instruction.
121 // instruction
[all...] |
