1 // events from file events/mips/34K/events 2 {0x0, CTR(0) | CTR(1), 0, "CYCLES", 3 "0-0 Cycles"}, 4 {0x1, CTR(0) | CTR(1), 0, "INSTRUCTIONS", 5 "1-0 Instructions completed"}, 6 {0xb, CTR(0) | CTR(1), 0, "DCACHE_MISSES", 7 "11-0 Data cache misses"}, 8 {0x2, CTR(0), 0, "BRANCH_INSNS", 9 "2-0 Branch instructions (whether completed or mispredicted)"}, 10 {0x3, CTR(0), 0, "JR_31_INSNS", 11 "3-0 JR $31 (return) instructions executed"}, 12 {0x4, CTR(0), 0, "JR_NON_31_INSNS", 13 "4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)"}, 14 {0x5, CTR(0), 0, "ITLB_ACCESSES", 15 "5-0 Instruction micro-TLB accesses"}, 16 {0x6, CTR(0), 0, "DTLB_ACCESSES", 17 "6-0 Data micro-TLB accesses"}, 18 {0x7, CTR(0), 0, "JTLB_INSN_ACCESSES", 19 "7-0 Joint TLB instruction accesses"}, 20 {0x8, CTR(0), 0, "JTLB_DATA_ACCESSES", 21 "8-0 Joint TLB data (non-instruction) accesses"}, 22 {0x9, CTR(0), 0, "ICACHE_ACCESSES", 23 "9-0 Instruction cache accesses"}, 24 {0xa, CTR(0), 0, "DCACHE_ACCESSES", 25 "10-0 Data cache accesses"}, 26 {0xd, CTR(0), 0, "STORE_MISS_INSNS", 27 "13-0 Cacheable stores that miss in the cache"}, 28 {0xe, CTR(0), 0, "INTEGER_INSNS", 29 "14-0 Integer instructions completed"}, 30 {0xf, CTR(0), 0, "LOAD_INSNS", 31 "15-0 Load instructions completed (including FP)"}, 32 {0x10, CTR(0), 0, "J_JAL_INSNS", 33 "16-0 J/JAL instructions completed"}, 34 {0x11, CTR(0), 0, "NO_OPS_INSNS", 35 "17-0 no-ops completed, ie instructions writing $0"}, 36 {0x12, CTR(0), 0, "ALL_STALLS", 37 "18-0 Stall cycles, including ALU and IFU"}, 38 {0x13, CTR(0), 0, "SC_INSNS", 39 "19-0 SC instructions completed"}, 40 {0x14, CTR(0), 0, "PREFETCH_INSNS", 41 "20-0 PREFETCH instructions completed"}, 42 {0x15, CTR(0), 0, "L2_CACHE_WRITEBACKS", 43 "21-0 L2 cache lines written back to memory"}, 44 {0x16, CTR(0), 0, "L2_CACHE_MISSES", 45 "22-0 L2 cache accesses that missed in the cache"}, 46 {0x17, CTR(0), 0, "EXCEPTIONS_TAKEN", 47 "23-0 Exceptions taken"}, 48 {0x18, CTR(0), 0, "CACHE_FIXUP_CYCLES", 49 "24-0 Cache fixup cycles (specific to the 34K family microarchitecture)"}, 50 {0x19, CTR(0), 0, "IFU_STALLS", 51 "25-0 IFU stall cycles"}, 52 {0x1a, CTR(0), 0, "DSP_INSNS", 53 "26-0 DSP instructions completed"}, 54 {0x1c, CTR(0), 0, "POLICY_EVENTS", 55 "28-0 Implementation specific policy manager events"}, 56 {0x1d, CTR(0), 0, "ISPRAM_EVENTS", 57 "29-0 Implementation specific ISPRAM events"}, 58 {0x1e, CTR(0), 0, "COREEXTEND_EVENTS", 59 "30-0 Implementation specific CorExtend events"}, 60 {0x1f, CTR(0), 0, "YIELD_EVENTS", 61 "31-0 Implementation specific yield events"}, 62 {0x20, CTR(0), 0, "ITC_LOADS", 63 "32-0 ITC Loads"}, 64 {0x21, CTR(0), 0, "UNCACHED_LOAD_INSNS", 65 "33-0 Uncached load instructions"}, 66 {0x22, CTR(0), 0, "FORK_INSNS", 67 "34-0 Fork instructions completed"}, 68 {0x23, CTR(0), 0, "CP2_ARITH_INSNS", 69 "35-0 CP2 arithmetic instructions completed"}, 70 {0x25, CTR(0), 0, "ICACHE_MISS_STALLS", 71 "37-0 Stall cycles due to an instruction cache miss"}, 72 {0x27, CTR(0), 0, "DCACHE_MISS_CYCLES", 73 "39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline"}, 74 {0x28, CTR(0), 0, "UNCACHED_STALLS", 75 "40-0 Uncached stall cycles"}, 76 {0x29, CTR(0), 0, "MDU_STALLS", 77 "41-0 MDU stall cycles"}, 78 {0x2a, CTR(0), 0, "CP2_STALLS", 79 "42-0 CP2 stall cycles"}, 80 {0x2b, CTR(0), 0, "ISPRAM_STALLS", 81 "43-0 ISPRAM stall cycles"}, 82 {0x2c, CTR(0), 0, "CACHE_INSN_STALLS", 83 "44-0 Stall cycless due to CACHE instructions"}, 84 {0x2d, CTR(0), 0, "LOAD_USE_STALLS", 85 "45-0 Load to use stall cycles"}, 86 {0x2e, CTR(0), 0, "INTERLOCK_STALLS", 87 "46-0 Stall cycles due to return data from MFC0, RDHWR, and MFTR instructions"}, 88 {0x2f, CTR(0), 0, "RELAX_STALLS", 89 "47-0 Low power stall cycles (operations) as requested by the policy manager"}, 90 {0x30, CTR(0), 0, "IFU_FB_FULL_REFETCHES", 91 "48-0 Refetches due to cache misses while both fill buffers already allocated"}, 92 {0x31, CTR(0), 0, "EJTAG_INSN_TRIGGERS", 93 "49-0 EJTAG instruction triggerpoints"}, 94 {0x32, CTR(0), 0, "FSB_LESS_25_FULL", 95 "50-0 FSB < 25% full"}, 96 {0x33, CTR(0), 0, "FSB_OVER_50_FULL", 97 "51-0 FSB > 50% full"}, 98 {0x34, CTR(0), 0, "LDQ_LESS_25_FULL", 99 "52-0 LDQ < 25% full"}, 100 {0x35, CTR(0), 0, "LDQ_OVER_50_FULL", 101 "53-0 LDQ > 50% full"}, 102 {0x36, CTR(0), 0, "WBB_LESS_25_FULL", 103 "54-0 WBB < 25% full"}, 104 {0x37, CTR(0), 0, "WBB_OVER_50_FULL", 105 "55-0 WBB > 50% full"}, 106 {0x3e, CTR(0), 0, "READ_RESPONSE_LATENCY", 107 "62-0 Read latency from miss detection until critical dword of response is returned"}, 108 {0x402, CTR(1), 0, "MISPREDICTED_BRANCH_INSNS", 109 "2-1 Branch mispredictions"}, 110 {0x403, CTR(1), 0, "JR_31_MISPREDICTIONS", 111 "3-1 JR $31 mispredictions"}, 112 {0x404, CTR(1), 0, "JR_31_NO_PREDICTIONS", 113 "4-1 JR $31 not predicted (stack mismatch)."}, 114 {0x405, CTR(1), 0, "ITLB_MISSES", 115 "5-1 Instruction micro-TLB misses"}, 116 {0x406, CTR(1), 0, "DTLB_MISSES", 117 "6-1 Data micro-TLB misses"}, 118 {0x407, CTR(1), 0, "JTLB_INSN_MISSES", 119 "7-1 Joint TLB instruction misses"}, 120 {0x408, CTR(1), 0, "JTLB_DATA_MISSES", 121 "8-1 Joint TLB data (non-instruction) misses"}, 122 {0x409, CTR(1), 0, "ICACHE_MISSES", 123 "9-1 Instruction cache misses"}, 124 {0x40a, CTR(1), 0, "DCACHE_WRITEBACKS", 125 "10-1 Data cache lines written back to memory"}, 126 {0x40d, CTR(1), 0, "LOAD_MISS_INSNS", 127 "13-1 Cacheable load instructions that miss in the cache"}, 128 {0x40e, CTR(1), 0, "FPU_INSNS", 129 "14-1 FPU instructions completed (not including loads/stores)"}, 130 {0x40f, CTR(1), 0, "STORE_INSNS", 131 "15-1 Stores completed (including FP)"}, 132 {0x410, CTR(1), 0, "MIPS16_INSNS", 133 "16-1 MIPS16 instructions completed"}, 134 {0x411, CTR(1), 0, "INT_MUL_DIV_INSNS", 135 "17-1 Integer multiply/divide instructions completed"}, 136 {0x412, CTR(1), 0, "REPLAYED_INSNS", 137 "18-1 Replayed instructions"}, 138 {0x413, CTR(1), 0, "SC_INSNS_FAILED", 139 "19-1 SC instructions completed, but store failed (because the link bit had been cleared)"}, 140 {0x414, CTR(1), 0, "CACHE_HIT_PREFETCH_INSNS", 141 "20-1 PREFETCH instructions completed with cache hit"}, 142 {0x415, CTR(1), 0, "L2_CACHE_ACCESSES", 143 "21-1 Accesses to the L2 cache"}, 144 {0x416, CTR(1), 0, "L2_CACHE_SINGLE_BIT_ERRORS", 145 "22-1 Single bit errors corrected in L2"}, 146 {0x417, CTR(1), 0, "SINGLE_THREADED_CYCLES", 147 "23-1 Cycles while one and only one TC is eligible for scheduling"}, 148 {0x418, CTR(1), 0, "REFETCHED_INSNS", 149 "24-1 Replayed instructions sent back to IFU to be refetched"}, 150 {0x419, CTR(1), 0, "ALU_STALLS", 151 "25-1 ALU stall cycles"}, 152 {0x41a, CTR(1), 0, "ALU_DSP_SATURATION_INSNS", 153 "26-1 ALU-DSP saturation instructions"}, 154 {0x41b, CTR(1), 0, "MDU_DSP_SATURATION_INSNS", 155 "27-1 MDU-DSP saturation instructions"}, 156 {0x41c, CTR(1), 0, "CP2_EVENTS", 157 "28-1 Implementation specific CP2 events"}, 158 {0x41d, CTR(1), 0, "DSPRAM_EVENTS", 159 "29-1 Implementation specific DSPRAM events"}, 160 {0x41f, CTR(1), 0, "ITC_EVENT", 161 "31-1 Implementation specific yield event"}, 162 {0x421, CTR(1), 0, "UNCACHED_STORE_INSNS", 163 "33-1 Uncached store instructions"}, 164 {0x423, CTR(1), 0, "CP2_TO_FROM_INSNS", 165 "35-1 CP2 to/from instructions (moves, control, loads, stores)"}, 166 {0x425, CTR(1), 0, "DCACHE_MISS_STALLS", 167 "37-1 Stall cycles due to a data cache miss"}, 168 {0x427, CTR(1), 0, "L2_CACHE_MISS_CYCLES", 169 "39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline"}, 170 {0x428, CTR(1), 0, "ITC_STALLS", 171 "40-1 ITC stall cycles"}, 172 {0x429, CTR(1), 0, "FPU_STALLS", 173 "41-1 FPU stall cycles"}, 174 {0x42a, CTR(1), 0, "COREEXTEND_STALLS", 175 "42-1 CorExtend stall cycles"}, 176 {0x42b, CTR(1), 0, "DSPRAM_STALLS", 177 "43-1 DSPRAM stall cycles"}, 178 {0x42d, CTR(1), 0, "ALU_TO_AGEN_STALLS", 179 "45-1 ALU to AGEN stall cycles"}, 180 {0x42e, CTR(1), 0, "MISPREDICTION_STALLS", 181 "46-1 Branch mispredict stall cycles"}, 182 {0x430, CTR(1), 0, "FB_ENTRY_ALLOCATED_CYCLES", 183 "48-1 Cycles while at least one IFU fill buffer is allocated"}, 184 {0x431, CTR(1), 0, "EJTAG_DATA_TRIGGERS", 185 "49-1 EJTAG Data triggerpoints"}, 186 {0x432, CTR(1), 0, "FSB_25_50_FULL", 187 "50-1 FSB 25-50% full"}, 188 {0x433, CTR(1), 0, "FSB_FULL_STALLS", 189 "51-1 FSB full pipeline stall cycles"}, 190 {0x434, CTR(1), 0, "LDQ_25_50_FULL", 191 "52-1 LDQ 25-50% full"}, 192 {0x435, CTR(1), 0, "LDQ_FULL_STALLS", 193 "53-1 LDQ full pipeline stall cycles"}, 194 {0x436, CTR(1), 0, "WBB_25_50_FULL", 195 "54-1 WBB 25-50% full"}, 196 {0x437, CTR(1), 0, "WBB_FULL_STALLS", 197 "55-1 WBB full pipeline stall cycles"}, 198 {0x43e, CTR(1), 0, "READ_RESPONSE_COUNT", 199 "62-1 Read requests on miss detection"}, 200
