| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_ra.cpp | 227 void condenseDefs(Instruction *);
228 void condenseSrcs(Instruction *, const int first, const int last);
230 void addHazard(Instruction *i, const ValueRef *src);
232 void addConstraint(Instruction *, int s, int n);
233 bool detectConflict(Instruction *, int s);
240 std::list<Instruction *> constrList;
284 LValue *unspill(Instruction *usei, LValue *, Value *slot);
285 void spill(Instruction *defi, Value *slot, LValue *);
293 Instruction *insn = val->getUniqueInsn();
337 Instruction *phi, *mov
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_ra.cpp | 227 void condenseDefs(Instruction *);
228 void condenseSrcs(Instruction *, const int first, const int last);
230 void addHazard(Instruction *i, const ValueRef *src);
232 void addConstraint(Instruction *, int s, int n);
233 bool detectConflict(Instruction *, int s);
240 std::list<Instruction *> constrList;
284 LValue *unspill(Instruction *usei, LValue *, Value *slot);
285 void spill(Instruction *defi, Value *slot, LValue *);
293 Instruction *insn = val->getUniqueInsn();
337 Instruction *phi, *mov
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow.c | 181 * the instruction.
239 * Also, the writemask of the instruction is not taken into account.
283 * Calls a callback function for all register writes in the instruction,
317 * and the writemask of the instruction is not taken into account.
439 * and update the given instruction \p inst accordingly
728 * readers we jump to the BGNLOOP instruction
729 * and check each instruction until we get
823 * encounters an instruction that reads from @param writer and also a different
824 * instruction. Here are some examples:
826 * writer = instruction 0
[all...] |
| /external/llvm/docs/ |
| WritingAnLLVMBackend.rst | 30 characteristics, such as a RISC instruction set and straightforward calling
50 descriptions of code generation stages: Instruction Selection, Scheduling and
65 reference. For details about the ARM instruction set, refer to the `ARM
92 * Describe the instruction set of the target. Use TableGen to generate code
104 DAG-to-DAG instruction selection. Also write code in ``XXXISelLowering.cpp``
186 methods are named ``get*Info``, and are intended to obtain the instruction set
321 same way for some instruction. Typical examples are register classes for
323 instruction to use any register in a specified register class to perform the
324 instruction in a similar manner. Register classes allocate virtual registers
487 // default value 1 means a single instruction
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| AliasAnalysis.h | 143 /// the given instruction.
350 /// getModRefInfo - Return information about whether or not an instruction may
351 /// read or write the specified memory location. An instruction
353 ModRefResult getModRefInfo(const Instruction *I,
356 case Instruction::VAArg: return getModRefInfo((const VAArgInst*)I, Loc);
357 case Instruction::Load: return getModRefInfo((const LoadInst*)I, Loc);
358 case Instruction::Store: return getModRefInfo((const StoreInst*)I, Loc);
359 case Instruction::Fence: return getModRefInfo((const FenceInst*)I, Loc);
360 case Instruction::AtomicCmpXchg:
362 case Instruction::AtomicRMW
[all...] |
| TargetTransformInfo.h | 81 /// enumeration because it is expected that the cost of one IR instruction
87 /// cost and execution cost. A free instruction is typically one that folds
88 /// into another instruction. For example, reg-to-reg moves can often be
93 TCC_Basic = 1, ///< The cost of a typical 'add' instruction.
94 TCC_Expensive = 4 ///< The cost of a 'div' instruction on x86.
100 /// thus work for hypothetical queries before an instruction has even been
102 /// for a GEP instruction. Instead, use the dedicated getGEPCost interface as
159 /// This can estimate the cost of either a ConstantExpr or Instruction when
166 /// folded into a load or other instruction, but if they are used in some
184 /// instruction or equivalent in order to call the given function
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| LowerInvoke.cpp | 17 // abort(). If the program does dynamically use the unwind instruction, the
21 // support to the program at the cost of making the 'invoke' instruction
33 // support the invoke instruction yet" lowering pass.
173 // Insert a normal call instruction...
188 // Remove the invoke instruction now.
197 /// specified invoke instruction with a call.
230 Instruction* StackPtrLoad =
238 // Insert a normal call instruction.
282 // to a copy instruction in the entry block. This ensures that the argument
295 Instruction *EI = ExtractValueInst::Create(AI, 0, "",AfterAllocaInsertPt)
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow.c | 181 * the instruction.
239 * Also, the writemask of the instruction is not taken into account.
283 * Calls a callback function for all register writes in the instruction,
317 * and the writemask of the instruction is not taken into account.
439 * and update the given instruction \p inst accordingly
728 * readers we jump to the BGNLOOP instruction
729 * and check each instruction until we get
823 * encounters an instruction that reads from @param writer and also a different
824 * instruction. Here are some examples:
826 * writer = instruction 0
[all...] |
| /prebuilts/tools/common/m2/internal/net/sf/proguard/proguard-base/4.9/ |
| proguard-base-4.9-sources.jar | |
| /external/llvm/include/llvm/IR/ |
| IRBuilder.h | 33 /// 'InsertHelper' method that is called whenever an instruction is created by
36 /// By default, this inserts the instruction at the insertion point.
40 void InsertHelper(Instruction *I, const Twine &Name,
85 /// the specified instruction.
86 void SetInsertPoint(Instruction *I) {
103 Instruction *UseInst = cast<Instruction>(U.getUser());
122 /// specified instruction.
123 void SetInstDebugLocation(Instruction *I) const {
286 /// specified, it will be added to the instruction
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenMapTable.cpp | 1 //===- CodeGenMapTable.cpp - Instruction Mapping Table Generator ----------===//
30 // that can be used to retrieve the predicated form of the instruction by
32 // instruction as arguments.
44 // sort of relationship with the key instruction defined by the corresponding
70 // 4) For each key instruction, get the group of instructions that share the
71 // same key-value as the key instruction from RowInstrMap. Iterate over the list
74 // instruction from the group that matches all the values for the column.
114 // List of fields/attributes that are constant across all the instruction
119 // Ex: KeyCol = 'noPred' -- key instruction is non predicated
130 // Each instruction map must specify at least one column for it to be valid
[all...] |
| DFAPacketizerEmitter.cpp | 11 // to reason about whether an instruction can be added to a packet on a VLIW
62 // a set of instruction classes.
69 // with three instruction classes: L, M, and L_or_M.
70 // From the initial state (currentState = 0x00), if we add instruction class
73 // instruction
99 // canAddInsnClass - Returns true if an instruction of type InsnClass is a
100 // valid transition from this state, i.e., can an instruction of type InsnClass
237 // canAddInsnClass - Quickly verifies if an instruction of type InsnClass is a
238 // valid transition from this state i.e., can an instruction of type InsnClass
416 // Collect the instruction classes
[all...] |
| /art/runtime/entrypoints/portable/ |
| portable_trampoline_entrypoints.cc | 325 const Instruction* instr = Instruction::At(&code->insns_[dex_pc]);
326 Instruction::Code instr_code = instr->Opcode();
328 case Instruction::INVOKE_DIRECT:
332 case Instruction::INVOKE_DIRECT_RANGE:
336 case Instruction::INVOKE_STATIC:
340 case Instruction::INVOKE_STATIC_RANGE:
344 case Instruction::INVOKE_SUPER:
348 case Instruction::INVOKE_SUPER_RANGE:
352 case Instruction::INVOKE_VIRTUAL
[all...] |
| /art/runtime/entrypoints/quick/ |
| quick_trampoline_entrypoints.cc | 463 const Instruction* instr = Instruction::At(&code->insns_[dex_pc]);
464 Instruction::Code instr_code = instr->Opcode();
467 case Instruction::INVOKE_DIRECT:
471 case Instruction::INVOKE_DIRECT_RANGE:
475 case Instruction::INVOKE_STATIC:
479 case Instruction::INVOKE_STATIC_RANGE:
483 case Instruction::INVOKE_SUPER:
487 case Instruction::INVOKE_SUPER_RANGE:
491 case Instruction::INVOKE_VIRTUAL
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| RegisterPressure.h | 157 /// Track the current register pressure at some position in the instruction
193 /// Register pressure corresponds to liveness before this instruction
195 /// an instruction.
237 /// \brief Get the SlotIndex for the first nondebug instruction including or
241 /// Recede across the previous instruction.
244 /// Advance across the current instruction.
280 /// Consider the pressure increase caused by traversing this instruction
283 /// excess register units of that pressure set introduced by this instruction.
289 /// Consider the pressure increase caused by traversing this instruction
292 /// excess register units of that pressure set introduced by this instruction
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVLIWPacketizer.cpp | 11 // machine basic blocks. For each instruction I in BB, the packetizer consults
13 // packetizer checks if I depends on any instruction J in the current packet.
95 // Has the instruction been promoted to a dot-new instruction.
98 // Has the instruction been glued to allocframe.
101 // Has the feeder instruction been glued to new value jump.
104 // Check if there is a dependence between some instruction already in this
105 // packet and this instruction.
109 // schedule this instruction.
130 // isSoloInstruction - return true if instruction MI can not be packetize
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| JumpThreading.cpp | 189 // If the terminator is the only non-phi instruction, try to nuke it.
230 // Sum up the cost of each instruction until we get to the terminator. Don't
348 // If V is a non-instruction value, or an instruction in a different block,
350 Instruction *I = dyn_cast<Instruction>(V);
361 // "I" is a non-local compare-with-a-constant instruction. This would be
402 if (I->getOpcode() == Instruction::Or ||
403 I->getOpcode() == Instruction::And) {
413 if (I->getOpcode() == Instruction::Or
[all...] |
| /external/proguard/src/proguard/optimize/peephole/ |
| MethodInliner.java | 29 import proguard.classfile.instruction.*;
30 import proguard.classfile.instruction.visitor.InstructionVisitor;
320 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction)
322 codeAttributeComposer.appendInstruction(offset, instruction.shrink());
328 // Are we inlining this instruction?
340 // Are we not at the last instruction?
343 // Replace the return instruction by a branch instruction.
344 Instruction branchInstruction
[all...] |
| /ndk/docs/text/ |
| CPU-ARCH-ABIS.text | 15 - the CPU instruction set that the machine code should use
47 the ARMv5TE instruction set. Please refer to following documentation for
87 include a few CPU instruction set extensions as described in the following
92 The instruction extensions supported by this Android-specific ABI are:
94 - The Thumb-2 instruction set extension.
128 This is the name of an ABI for CPUs supporting the instruction set
137 which targets Pentium Pro instruction set, according to the GCC
138 documentation, plus the MMX, SSE, SSE2 and SSE3 instruction set
152 The ABI does *not* include any other optional IA-32 instruction set
155 - the MOVBE instruction
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| BasicBlockList.java | 102 * Gets the total instruction count for this instance. This is the
103 * sum of the instruction counts of each block.
105 * @return {@code >= 0;} the total instruction count
122 * Gets the total instruction count for this instance, ignoring
125 * @return {@code >= 0;} the total instruction count
170 * Visits each instruction of each block in the list, in order.
186 * the registers in each instruction are offset by the given
312 * Instruction visitor class for counting registers used.
368 * @param insn {@code non-null;} instruction being visited
|
| /dalvik/dx/src/com/android/dx/cf/code/ |
| BytecodeArray.java | 101 * Parses each instruction in the array, in order.
104 * each instruction
120 * Finds the offset to each instruction in the bytecode array. The
142 * in the set, clearing it, and parsing and visiting the instruction at
149 * each instruction
168 * Parses the instruction at the indicated offset. Indicate the
170 * number of bytes consumed by the instruction.
213 * instruction
215 * @return the length of the instruction, in bytes
[all...] |
| /dalvik/dx/src/com/android/dx/rop/code/ |
| BasicBlockList.java | 102 * Gets the total instruction count for this instance. This is the
103 * sum of the instruction counts of each block.
105 * @return {@code >= 0;} the total instruction count
122 * Gets the total instruction count for this instance, ignoring
125 * @return {@code >= 0;} the total instruction count
169 * Visits each instruction of each block in the list, in order.
185 * the registers in each instruction are offset by the given
310 * Instruction visitor class for counting registers used.
366 * @param insn {@code non-null;} instruction being visited
|
| /dalvik/vm/mterp/c/ |
| header.cpp | 35 #ifdef WITH_INSTR_CHECKS /* instruction-level paranoia (slow!) */
78 * Export another copy of the PC on every instruction; this is largely
94 * We don't advance the program counter until we finish an instruction or
265 * want to load 16 bits at a time from the instruction stream -- it's more
273 * Extract instruction byte from 16-bit fetch (_inst is a u2).
283 * Extract the "vA, vB" 4-bit registers from the instruction word (_inst is u2).
289 * Get the 8-bit "vAA" 8-bit register index from the instruction word.
313 * Use this to check for NULL when the instruction handler calls into
345 * Use this to check for NULL when the instruction handler doesn't do
|
| /external/chromium_org/native_client_sdk/src/examples/api/file_io/ |
| file_io.cc | 101 // Parse message into: instruction file_name_length file_name [file_text]
103 std::string instruction; local
108 reader >> instruction >> file_name_length;
118 // Dispatch the instruction
119 if (instruction == kLoadPrefix) {
122 } else if (instruction == kSavePrefix) {
128 } else if (instruction == kDeletePrefix) {
131 } else if (instruction == kListPrefix) {
135 } else if (instruction == kMakeDirPrefix) {
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_wm_pass0.c | 56 /** return pointer to a newly allocated instruction */
60 memset(&c->instruction[c->nr_insns], 0, sizeof(*c->instruction));
61 return &c->instruction[c->nr_insns++];
241 * Straight translation to internal instruction format
295 newref->insn = insn - c->instruction;
321 /* Copy some data out of the instruction
406 * an instruction produces duplicate values (eg DP3), all are given
424 /* Optimize away moves, otherwise emit translated instruction:
|
