| /external/v8/build/ |
| common.gypi | 66 'mips_arch_variant%': 'mips32r2',
188 ['mips_arch_variant=="mips32r2"', {
189 'cflags': ['-mips32r2', '-Wa,-mips32r2'],
215 ['mips_arch_variant=="mips32r2"', {
|
| /system/core/libpixelflinger/arch-mips/ |
| t32cb16blend.S | 94 DBG .set mips32r2
162 DBG .set mips32r2
258 DBG .set mips32r2
|
| /bionic/libc/kernel/arch-mips/asm/ |
| mipsmtregs.h | 159 #define mftc0(rt,sel) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " # mftc0 $1, $" #rt ", " #sel " \n" " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
160 #define mftgpr(rt) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips32r2 \n" " # mftgpr $1," #rt " \n" " .word 0x41000820 | (" #rt " << 16) \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
162 #define mttgpr(rd,v) do { __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttgpr $1, " #rd " \n" " .word 0x41810020 | (" #rd " << 11) \n" " .set pop \n" : : "r" (v)); } while (0)
164 #define mttc0(rd, sel, v) ({ __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttc0 %0," #rd ", " #sel " \n" " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" " .set pop \n" : : "r" (v)); })
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| mipsmtregs.h | 159 #define mftc0(rt,sel) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " # mftc0 $1, $" #rt ", " #sel " \n" " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
160 #define mftgpr(rt) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips32r2 \n" " # mftgpr $1," #rt " \n" " .word 0x41000820 | (" #rt " << 16) \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
162 #define mttgpr(rd,v) do { __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttgpr $1, " #rd " \n" " .word 0x41810020 | (" #rd " << 11) \n" " .set pop \n" : : "r" (v)); } while (0)
164 #define mttc0(rd, sel, v) ({ __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttc0 %0," #rd ", " #sel " \n" " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" " .set pop \n" : : "r" (v)); })
|
| /external/clang/test/Driver/ |
| mips-as.c | 50 // RUN: %clang -target mips-linux-gnu -march=mips32r2 -### \
53 // MIPS-32R2: as{{(.exe)?}}" "-march" "mips32r2" "-mabi" "32" "-EB"
60 // RUN: %clang -target mips-linux-gnu -mips32r2 -### \
63 // MIPS-ALIAS-32R2: as{{(.exe)?}}" "-march" "mips32r2" "-mabi" "32" "-EB"
|
| android-standalone.cpp | 37 // RUN: -march=mips32 -mips32r2 \
53 // RUN: -mips32 -march=mips32r2 \
|
| /external/llvm/test/MC/Mips/ |
| micromips-shift-instructions.s | 1 # RUN: llvm-mc %s -triple=mipsel -show-encoding -mcpu=mips32r2 -mattr=micromips | FileCheck %s
|
| mips-relocations.s | 1 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| mipsmtregs.h | 159 #define mftc0(rt,sel) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " # mftc0 $1, $" #rt ", " #sel " \n" " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
160 #define mftgpr(rt) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips32r2 \n" " # mftgpr $1," #rt " \n" " .word 0x41000820 | (" #rt " << 16) \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
162 #define mttgpr(rd,v) do { __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttgpr $1, " #rd " \n" " .word 0x41810020 | (" #rd " << 11) \n" " .set pop \n" : : "r" (v)); } while (0)
164 #define mttc0(rd, sel, v) ({ __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttc0 %0," #rd ", " #sel " \n" " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" " .set pop \n" : : "r" (v)); })
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
| mipsmtregs.h | 159 #define mftc0(rt,sel) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " # mftc0 $1, $" #rt ", " #sel " \n" " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
160 #define mftgpr(rt) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips32r2 \n" " # mftgpr $1," #rt " \n" " .word 0x41000820 | (" #rt " << 16) \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
162 #define mttgpr(rd,v) do { __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttgpr $1, " #rd " \n" " .word 0x41810020 | (" #rd " << 11) \n" " .set pop \n" : : "r" (v)); } while (0)
164 #define mttc0(rd, sel, v) ({ __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttc0 %0," #rd ", " #sel " \n" " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" " .set pop \n" : : "r" (v)); })
|
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/ |
| mipsmtregs.h | 159 #define mftc0(rt,sel) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " # mftc0 $1, $" #rt ", " #sel " \n" " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
160 #define mftgpr(rt) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips32r2 \n" " # mftgpr $1," #rt " \n" " .word 0x41000820 | (" #rt " << 16) \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
162 #define mttgpr(rd,v) do { __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttgpr $1, " #rd " \n" " .word 0x41810020 | (" #rd " << 11) \n" " .set pop \n" : : "r" (v)); } while (0)
164 #define mttc0(rd, sel, v) ({ __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttc0 %0," #rd ", " #sel " \n" " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" " .set pop \n" : : "r" (v)); })
|
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/ |
| mipsmtregs.h | 159 #define mftc0(rt,sel) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " # mftc0 $1, $" #rt ", " #sel " \n" " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
160 #define mftgpr(rt) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips32r2 \n" " # mftgpr $1," #rt " \n" " .word 0x41000820 | (" #rt " << 16) \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
162 #define mttgpr(rd,v) do { __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttgpr $1, " #rd " \n" " .word 0x41810020 | (" #rd " << 11) \n" " .set pop \n" : : "r" (v)); } while (0)
164 #define mttc0(rd, sel, v) ({ __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttc0 %0," #rd ", " #sel " \n" " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" " .set pop \n" : : "r" (v)); })
|
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/ |
| mipsmtregs.h | 159 #define mftc0(rt,sel) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " # mftc0 $1, $" #rt ", " #sel " \n" " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
160 #define mftgpr(rt) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips32r2 \n" " # mftgpr $1," #rt " \n" " .word 0x41000820 | (" #rt " << 16) \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; })
162 #define mttgpr(rd,v) do { __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttgpr $1, " #rd " \n" " .word 0x41810020 | (" #rd " << 11) \n" " .set pop \n" : : "r" (v)); } while (0)
164 #define mttc0(rd, sel, v) ({ __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttc0 %0," #rd ", " #sel " \n" " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" " .set pop \n" : : "r" (v)); })
|
| /external/v8/ |
| SConstruct | 185 'mips_arch_variant:mips32r2': {
194 'mips_arch_variant:mips32r2': {
195 'CCFLAGS': ['-mips32r2', '-Wa,-mips32r2']
355 'mips_arch_variant:mips32r2': {
554 'mips_arch_variant:mips32r2': {
563 'mips_arch_variant:mips32r2': {
564 'CCFLAGS': ['-mips32r2', '-Wa,-mips32r2']
715 'mips_arch_variant:mips32r2':
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCTargetDesc.cpp | 57 } else if (CPU == "mips32r2") {
58 MipsArchFeature = "+mips32r2";
|
| /external/llvm/lib/Target/Mips/ |
| MipsSubtarget.h | 44 Mips32, Mips32r2, Mips64, Mips64r2
153 bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
|
| /external/chromium_org/v8/build/ |
| toolchain.gypi | 59 'mips_arch_variant%': 'mips32r2',
292 ['mips_arch_variant=="mips32r2"', {
293 'cflags': ['-mips32r2', '-Wa,-mips32r2'],
320 ['mips_arch_variant=="mips32r2"', {
|
| /external/kernel-headers/original/asm-mips/ |
| pgtable-bits.h | 126 #define _CACHE_CACHABLE_COHERENT (5<<_CACHE_SHIFT) /* MIPS32R2 CMP */
|
| /external/llvm/test/CodeGen/Mips/ |
| fabs.ll | 2 ; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2
|
| fcopysign.ll | 2 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2
|
| fp-indexed-ls.ll | 1 ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
|
| /external/qemu/ |
| qemu-timer.h | 264 * binutils wants to use rdhwr only on mips32r2
271 ".set mips32r2\n\t" \
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 70 #define mips32r2 1 macro
72 #define mips32r2 0 macro
400 case ROR: if (mips32r2) {
511 case ROR: if (mips32r2) {
543 case ROR: if (mips32r2) {
[all...] |
| /build/core/combo/ |
| TARGET_linux-mips.mk | 21 # than mips32r2-fp. Each value should correspond to a file named
34 TARGET_ARCH_VARIANT := mips32r2-fp
|
| /dalvik/vm/mterp/mips/ |
| header.S | 13 #define MIPS32R2
141 #ifndef MIPS32R2
|
