| /external/llvm/test/MC/AArch64/ |
| trace-regs-diagnostics.s | 13 msr trcstatr, x0
14 msr trcidr8, x13
15 msr trcidr9, x25
16 msr trcidr10, x2
17 msr trcidr11, x19
18 msr trcidr12, x15
19 msr trcidr13, x24
20 msr trcidr0, x20
21 msr trcidr1, x5
22 msr trcidr2, x1
[all...] |
| trace-regs.s | 419 msr trcoslar, x28
420 msr trclar, x14
421 msr trcprgctlr, x10
422 msr trcprocselr, x27
423 msr trcconfigr, x24
424 msr trcauxctlr, x8
425 msr trceventctl0r, x16
426 msr trceventctl1r, x27
427 msr trcstallctlr, x26
428 msr trctsctlr, x
[all...] |
| gicv3-regs.s | 116 msr icc_eoir1_el1, x27
117 msr icc_eoir0_el1, x5
118 msr icc_dir_el1, x13
119 msr icc_sgi1r_el1, x21
120 msr icc_asgi1r_el1, x25
121 msr icc_sgi0r_el1, x28
122 msr icc_bpr1_el1, x7
123 msr icc_bpr0_el1, x9
124 msr icc_pmr_el1, x29
125 msr icc_ctlr_el1, x2
[all...] |
| gicv3-regs-diagnostics.s | 30 msr icc_iar1_el1, x16
31 msr icc_iar0_el1, x19
32 msr icc_hppir1_el1, x29
33 msr icc_hppir0_el1, x14
34 msr icc_rpr_el1, x6
35 msr ich_vtr_el2, x8
36 msr ich_eisr_el2, x22
37 msr ich_elsr_el2, x8
39 // CHECK-NEXT: msr icc_iar1_el1, x16
42 // CHECK-NEXT: msr icc_iar0_el1, x1
[all...] |
| /external/llvm/test/MC/ARM/ |
| thumb2-mclass.s | 43 @ MSR
46 msr apsr, r0
47 msr apsr_nzcvq, r0
48 msr apsr_g, r0
49 msr apsr_nzcvqg, r0
50 msr iapsr, r0
51 msr iapsr_nzcvq, r0
52 msr iapsr_g, r0
53 msr iapsr_nzcvqg, r0
54 msr eapsr, r
[all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| trace-regs.txt | 404 # CHECK: msr trcoslar, x28
406 # CHECK: msr trclar, x14
408 # CHECK: msr trcprgctlr, x10
410 # CHECK: msr trcprocselr, x27
412 # CHECK: msr trcconfigr, x24
414 # CHECK: msr trcauxctlr, x8
416 # CHECK: msr trceventctl0r, x16
418 # CHECK: msr trceventctl1r, x27
420 # CHECK: msr trcstallctlr, x26
422 # CHECK: msr trctsctlr, x
[all...] |
| gicv3-regs.txt | 116 # CHECK: msr icc_eoir1_el1, x27
118 # CHECK: msr icc_eoir0_el1, x5
120 # CHECK: msr icc_dir_el1, x13
122 # CHECK: msr icc_sgi1r_el1, x21
124 # CHECK: msr icc_asgi1r_el1, x25
126 # CHECK: msr icc_sgi0r_el1, x28
128 # CHECK: msr icc_bpr1_el1, x7
130 # CHECK: msr icc_bpr0_el1, x9
132 # CHECK: msr icc_pmr_el1, x29
134 # CHECK: msr icc_ctlr_el1, x2
[all...] |
| /prebuilts/ndk/4/platforms/android-5/arch-x86/usr/include/asm/ |
| msr.h | 15 #include <asm/msr-index.h>
28 #define rdmsr(msr,val1,val2) __asm__ __volatile__("rdmsr" : "=a" (val1), "=d" (val2) : "c" (msr))
30 #define rdmsrl(msr,val) do { unsigned long a__,b__; __asm__ __volatile__("rdmsr" : "=a" (a__), "=d" (b__) : "c" (msr)); val = a__ | (b__<<32); } while(0)
32 #define wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : : "c" (msr), "a" (val1), "d" (val2))
34 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
|
| /prebuilts/ndk/4/platforms/android-8/arch-x86/usr/include/asm/ |
| msr.h | 15 #include <asm/msr-index.h>
28 #define rdmsr(msr,val1,val2) __asm__ __volatile__("rdmsr" : "=a" (val1), "=d" (val2) : "c" (msr))
30 #define rdmsrl(msr,val) do { unsigned long a__,b__; __asm__ __volatile__("rdmsr" : "=a" (a__), "=d" (b__) : "c" (msr)); val = a__ | (b__<<32); } while(0)
32 #define wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : : "c" (msr), "a" (val1), "d" (val2))
34 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
|
| /prebuilts/ndk/6/platforms/android-9/arch-x86/usr/include/asm/ |
| msr.h | 15 #include <asm/msr-index.h>
28 #define rdmsr(msr,val1,val2) __asm__ __volatile__("rdmsr" : "=a" (val1), "=d" (val2) : "c" (msr))
30 #define rdmsrl(msr,val) do { unsigned long a__,b__; __asm__ __volatile__("rdmsr" : "=a" (a__), "=d" (b__) : "c" (msr)); val = a__ | (b__<<32); } while(0)
32 #define wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : : "c" (msr), "a" (val1), "d" (val2))
34 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
|
| /prebuilts/ndk/7/platforms/android-14/arch-x86/usr/include/asm/ |
| msr.h | 15 #include <asm/msr-index.h>
28 #define rdmsr(msr,val1,val2) __asm__ __volatile__("rdmsr" : "=a" (val1), "=d" (val2) : "c" (msr))
30 #define rdmsrl(msr,val) do { unsigned long a__,b__; __asm__ __volatile__("rdmsr" : "=a" (a__), "=d" (b__) : "c" (msr)); val = a__ | (b__<<32); } while(0)
32 #define wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : : "c" (msr), "a" (val1), "d" (val2))
34 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
|
| /prebuilts/ndk/7/platforms/android-9/arch-x86/usr/include/asm/ |
| msr.h | 15 #include <asm/msr-index.h>
28 #define rdmsr(msr,val1,val2) __asm__ __volatile__("rdmsr" : "=a" (val1), "=d" (val2) : "c" (msr))
30 #define rdmsrl(msr,val) do { unsigned long a__,b__; __asm__ __volatile__("rdmsr" : "=a" (a__), "=d" (b__) : "c" (msr)); val = a__ | (b__<<32); } while(0)
32 #define wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : : "c" (msr), "a" (val1), "d" (val2))
34 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
|
| /external/libgsm/src/ |
| decode.c | 24 register word msr = S->msr; local
29 tmp = GSM_MULT_R( msr, 28180 );
30 msr = GSM_ADD(*s, tmp); /* Deemphasis */
31 *s = GSM_ADD(msr, msr) & 0xFFF8; /* Truncation & Upscaling */
33 S->msr = msr;
|
| /external/kernel-headers/original/asm-x86/ |
| msr.h | 4 #include <asm/msr-index.h>
17 static inline unsigned long long native_read_msr(unsigned int msr)
21 asm volatile("rdmsr" : "=A" (val) : "c" (msr));
25 static inline unsigned long long native_read_msr_safe(unsigned int msr,
40 : "c" (msr), "i" (-EFAULT));
45 static inline void native_write_msr(unsigned int msr, unsigned long long val)
47 asm volatile("wrmsr" : : "c" (msr), "A"(val));
50 static inline int native_write_msr_safe(unsigned int msr,
64 : "c" (msr), "0" ((u32)val), "d" ((u32)(val>>32)),
93 #define rdmsr(msr,val1,val2)
[all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| thumb-MSR-MClass.txt | 3 # CHECK: msr primask, r0
|
| /external/oprofile/module/ia64/ |
| op_ia64_model.h | 3 * interface to ia64 model-specific MSR operations
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/ |
| msr.h | 4 #include <asm/msr-index.h>
23 #define rdmsr(msr,val1,val2) \
26 : "c" (msr))
29 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
32 : "c" (msr)); \
36 #define wrmsr(msr,val1,val2) \
39 : "c" (msr), "a" (val1), "d" (val2))
41 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
| msr.h | 4 #include <asm/msr-index.h>
23 #define rdmsr(msr,val1,val2) \
26 : "c" (msr))
29 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
32 : "c" (msr)); \
36 #define wrmsr(msr,val1,val2) \
39 : "c" (msr), "a" (val1), "d" (val2))
41 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
| msr.h | 4 #include <asm/msr-index.h>
23 #define rdmsr(msr,val1,val2) \
26 : "c" (msr))
29 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
32 : "c" (msr)); \
36 #define wrmsr(msr,val1,val2) \
39 : "c" (msr), "a" (val1), "d" (val2))
41 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
|
| /external/clang/test/CodeGen/ |
| x86_32-inline-asm.c | 12 uint32_t msr = 0x8b; local
16 : "c" (msr),
|
| /bionic/libc/kernel/arch-arm/asm/ |
| locks.h | 35 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
36 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
37 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
41 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
42 #define __up_op_write(ptr,wake) ({ __asm__ __volatile__( "@ up_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", " (…)
[all...] |
| /development/ndk/platforms/android-3/arch-arm/include/asm/ |
| locks.h | 36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
47 #define __up_op_write(ptr,wake) ({ __asm__ __volatile__( "@ up_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", " (…)
[all...] |
| /external/kernel-headers/original/asm-arm/ |
| locks.h | 148 " msr cpsr_c, lr\n" \
152 " msr cpsr_c, ip\n" \
168 " msr cpsr_c, lr\n" \
172 " msr cpsr_c, ip\n" \
191 " msr cpsr_c, lr\n" \
195 " msr cpsr_c, ip\n" \
218 " msr cpsr_c, lr\n" \
222 " msr cpsr_c, ip\n" \
237 " msr cpsr_c, lr\n" \
241 " msr cpsr_c, ip\n"
[all...] |
| /prebuilts/ndk/4/platforms/android-3/arch-arm/usr/include/asm/ |
| locks.h | 36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
47 #define __up_op_write(ptr,wake) ({ __asm__ __volatile__( "@ up_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", " (…)
[all...] |
| /prebuilts/ndk/4/platforms/android-4/arch-arm/usr/include/asm/ |
| locks.h | 36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
47 #define __up_op_write(ptr,wake) ({ __asm__ __volatile__( "@ up_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", " (…)
[all...] |
