| /external/llvm/test/CodeGen/ARM/ |
| vmul.ll | 44 %tmp3 = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
89 %tmp3 = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
93 declare <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
94 declare <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
166 %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
186 %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
206 %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
226 %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
246 %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
266 %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2
[all...] |
| popcnt.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
141 %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
149 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
157 %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
165 %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
173 %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
181 %tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
185 declare <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8>) nounwind readnone
186 declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone
187 declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) nounwind readnon
[all...] |
| vadd.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
98 %tmp3 = call <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
107 %tmp3 = call <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
116 %tmp3 = call <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
120 declare <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
121 declare <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
122 declare <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
129 %tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
138 %tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
147 %tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2
[all...] |
| vsub.ll | 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
98 %tmp3 = call <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
107 %tmp3 = call <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
116 %tmp3 = call <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
120 declare <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
121 declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
122 declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
129 %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
138 %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
147 %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2
[all...] |
| 2012-01-23-PostRA-LICM.ll | 32 %tmp16 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp11) nounwind
33 %tmp17 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp16, <4 x float> %tmp11) nounwind
35 %tmp19 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp18, <4 x float> %tmp11) nounwind
38 %tmp22 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp21, <4 x float> undef) nounwind
51 %tmp34 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> undef, <4 x float> %tmp28) nounwind
73 %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind
97 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
99 declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
101 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
|
| 2012-01-24-RegSequenceLiveRange.ll | 55 tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %0, i32 4) nounwind
56 tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %2, i32 4) nounwind
66 tail call void @llvm.arm.neon.vst2.v4f32(i8* %p, <4 x float> undef, <4 x float> undef, i32 4)
71 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
72 declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
|
| coalesce-subregs.ll | 17 %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
21 tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> undef, i32 4)
30 %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
34 %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
36 tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> %vld2215, i32 4)
45 %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
55 %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
58 tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %qq0.0.1.0, <4 x float> %vld2215, i32 4)
67 declare { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8*, i32) nounwind readonly
68 declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwin
[all...] |
| neon_spill.ll | 25 call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind
43 call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind
47 declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
|
| 2010-05-21-BuildVector.ll | 39 tail call void @llvm.arm.neon.vst1.v4f32(i8* %20, <4 x float> %19, i32 1)
43 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
|
| dagcombine-concatvector.ll | 19 tail call void @llvm.arm.neon.vst1.v16i8(i8* %arg, <16 x i8> %tmp7, i32 2)
23 declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>, i32)
|
| /ndk/tests/build/check-armeabi-v7a-prebuilts/ |
| build.sh | 47 # neon
54 # In addition, NEON requires VFPv3-D32
77 # neon VFPv3 32
86 # neon VFPv3 32
106 # - When using 'neon', binutils-2.21 will also add a new tag named
112 # (i.e. no NEON, and only 16 hardware registers being used).
181 echo " found tags: CPU names:'$CPU_NAMES' VFP:'$VFP_ARCHS' NEON:'$NEON_ARCHS'"
183 # Clearly, any trace of NEON is a deal-breaker!
185 1>&2 echo "PANIC: Binary file should not contain NEON instructions: $1"
|
| /external/chromium_org/third_party/skia/gyp/ |
| opts.gyp | 142 # NEON code must be compiled with -mfpu=neon which also affects scalar
143 # code. To support dynamic NEON code paths, we need to build all
144 # NEON-specific sources in a separate static library. The situation
165 '-mfpu=neon',
|
| /external/clang/test/Driver/ |
| linux-as.c | 13 // RUN: %clang -target arm-linux -mfpu=neon -### \
16 // CHECK-ARM-MFPU: as{{(.exe)?}}" "-mfloat-abi=soft" "-mfpu=neon"
23 // RUN: %clang -target arm-linux -mcpu=cortex-a8 -mfpu=neon -march=armv7-a -### \
26 // CHECK-ARM-ALL: as{{(.exe)?}}" "-mfloat-abi=soft" "-march=armv7-a" "-mcpu=cortex-a8" "-mfpu=neon"
31 // CHECK-ARM-TARGET: as{{(.exe)?}}" "-mfpu=neon" "-mfloat-abi=soft" "-mcpu=cortex-a8"
|
| /external/skia/gyp/ |
| opts.gyp | 142 # NEON code must be compiled with -mfpu=neon which also affects scalar
143 # code. To support dynamic NEON code paths, we need to build all
144 # NEON-specific sources in a separate static library. The situation
165 '-mfpu=neon',
|
| /external/libvpx/libvpx/vp9/common/ |
| vp9_rtcd_defs.sh | 194 specialize vp9_mb_lpf_vertical_edge_w sse2 neon dspr2
197 specialize vp9_mbloop_filter_vertical_edge sse2 neon dspr2
200 specialize vp9_loop_filter_vertical_edge mmx neon dspr2
203 specialize vp9_mb_lpf_horizontal_edge_w sse2 avx2 neon dspr2
206 specialize vp9_mbloop_filter_horizontal_edge sse2 neon dspr2
209 specialize vp9_loop_filter_horizontal_edge mmx neon dspr2
245 specialize vp9_convolve_copy $sse2_x86inc neon dspr2
248 specialize vp9_convolve_avg $sse2_x86inc neon dspr2
251 specialize vp9_convolve8 sse2 ssse3 neon dspr2
254 specialize vp9_convolve8_horiz sse2 ssse3 neon dspr
[all...] |
| /bionic/libc/arch-arm/krait/bionic/ |
| memset.S | 35 * instructions, that supports neon instructions, and that supports
36 * unaligned neon instruction accesses to memory.
39 .fpu neon
|
| /device/asus/flo/ |
| BoardConfigCommon.mk | 17 TARGET_GLOBAL_CFLAGS += -mfpu=neon -mfloat-abi=softfp
18 TARGET_GLOBAL_CPPFLAGS += -mfpu=neon -mfloat-abi=softfp
23 TARGET_ARCH_VARIANT := armv7-a-neon
|
| /device/lge/mako/ |
| BoardConfig.mk | 17 TARGET_GLOBAL_CFLAGS += -mfpu=neon -mfloat-abi=softfp
18 TARGET_GLOBAL_CPPFLAGS += -mfpu=neon -mfloat-abi=softfp
23 TARGET_ARCH_VARIANT := armv7-a-neon
|
| /external/chromium_org/third_party/skia/src/opts/ |
| memset16_neon.S | 9 Neon memset: Attempts to do a memset with Neon registers if possible,
19 .fpu neon
|
| /external/skia/src/opts/ |
| memset16_neon.S | 9 Neon memset: Attempts to do a memset with Neon registers if possible,
19 .fpu neon
|
| /ndk/tests/build/build-mode/jni/ |
| Android.mk | 39 # We build 8 armeabi-v7a binaries because we need to check neon as well
72 LOCAL_SRC_FILES := main.c.neon
93 LOCAL_SRC_FILES := main.c.arm.neon
|
| /external/chromium_org/skia/ |
| skia_library_opts.gyp | 74 # The neon assembly contains conditional instructions which
205 # NEON code must be compiled with -mfpu=neon which also affects scalar
206 # code. To support dynamic NEON code paths, we need to build all
207 # NEON-specific sources in a separate static library. The situation
229 '-mfpu=neon',
|
| /external/llvm/test/CodeGen/Thumb2/ |
| machine-licm.ll | 62 %tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1, i32 1)
63 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %tmp2)
65 call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3, i32 1)
76 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
78 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
80 declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
|
| /bionic/libc/arch-arm/cortex-a9/bionic/ |
| memcpy.S | 34 * instructions, that supports neon instructions, and that has a 32 byte
39 .fpu neon
|
| /external/chromium_org/third_party/libwebp/ |
| libwebp.gyp | 77 # behavior similar to *.c.neon in an Android.mk
79 'cflags': [ '-mfpu=neon' ],
|
