| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.c | 53 * @param type - The opcode type (i.e., how many bytes it has).
56 * @param opcode - The last byte of the instruction's opcode, not counting
62 uint8_t opcode) {
86 return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
96 * @param opcode - See modRMRequired().
102 uint8_t opcode,
108 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
111 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
114 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_program_alu.c | 44 rc_opcode Opcode, struct rc_sub_instruction * base,
53 fpi->U.I.Opcode = Opcode;
61 rc_opcode Opcode, struct rc_sub_instruction * base,
71 fpi->U.I.Opcode = Opcode;
80 rc_opcode Opcode, struct rc_sub_instruction * base,
91 fpi->U.I.Opcode = Opcode;
199 const struct rc_opcode_info *info = rc_get_opcode_info(inst->U.I.Opcode);
[all...] |
| radeon_opcodes.h | 243 rc_opcode Opcode;
269 static inline const struct rc_opcode_info * rc_get_opcode_info(rc_opcode opcode)
271 assert((unsigned int)opcode < MAX_RC_OPCODE);
272 assert(rc_opcodes[opcode].Opcode == opcode);
274 return &rc_opcodes[opcode];
|
| /external/proguard/src/proguard/classfile/instruction/ |
| Instruction.java | 660 public byte opcode; field in class:Instruction
664 * Returns the canonical opcode of this instruction, i.e. typically the
665 * opcode whose extension has been removed.
669 return opcode;
695 // Write the wide opcode, if necessary.
701 // Write the opcode.
702 code[offset++] = opcode;
710 * Returns whether the instruction is wide, i.e. preceded by a wide opcode.
720 * Reads the data following the instruction opcode.
726 * Writes data following the instruction opcode
[all...] |
| /frameworks/base/tools/layoutlib/create/src/com/android/tools/layoutlib/create/ |
| DelegateMethodAdapter2.java | 349 public void visitInsn(int opcode) {
351 mOrgWriter.visitInsn(opcode);
370 public void visitMethodInsn(int opcode, String owner, String name, String desc) {
372 mOrgWriter.visitMethodInsn(opcode, owner, name, desc);
377 public void visitFieldInsn(int opcode, String owner, String name, String desc) {
379 mOrgWriter.visitFieldInsn(opcode, owner, name, desc);
398 public void visitIntInsn(int opcode, int operand) {
400 mOrgWriter.visitIntInsn(opcode, operand);
405 public void visitJumpInsn(int opcode, Label label) {
407 mOrgWriter.visitJumpInsn(opcode, label)
[all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 24 * opcode: ArmOpcode enum
25 * skeleton: pre-designated bit-pattern for this opcode
39 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \
42 {k3, k3s, k3e}}, opcode, flags, name, fmt, size}
[all...] |
| target_arm.cc | 125 uint64_t flags = ArmMir2Lir::EncodingMap[lir->opcode].flags;
126 int opcode = lir->opcode; local
181 if (opcode == kThumbPush || opcode == kThumbPop) {
183 if ((opcode == kThumbPush) && (lir->use_mask & r8Mask)) {
186 } else if ((opcode == kThumbPop) && (lir->def_mask & r8Mask)) {
249 static char* DecodeRegList(int opcode, int vector, char* buf) {
256 if (opcode == kThumbPush && i == 8) {
258 } else if (opcode == kThumbPop && i == 8)
[all...] |
| /cts/tools/dasm/src/dasm/ |
| DopInfo.java | 59 public String name; // opcode name
60 public Dop opcode; // its opcode field in class:DopInfo
113 * Adds new opcode to table
115 static private void add(String name, Dop opcode, String args) {
118 info.opcode = opcode;
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_opcodes.h | 243 rc_opcode Opcode;
269 static inline const struct rc_opcode_info * rc_get_opcode_info(rc_opcode opcode)
271 assert((unsigned int)opcode < MAX_RC_OPCODE);
272 assert(rc_opcodes[opcode].Opcode == opcode);
274 return &rc_opcodes[opcode];
|
| radeon_emulate_branches.c | 75 inst_mov->U.I.Opcode = RC_OPCODE_MOV;
165 inst_mov->U.I.Opcode = RC_OPCODE_MOV;
184 inst_cmp->U.I.Opcode = RC_OPCODE_CMP;
271 const struct rc_opcode_info * opcode; local
276 opcode = rc_get_opcode_info(inst->U.I.Opcode);
278 if (!opcode->HasDstReg)
295 inst_mov->U.I.Opcode = RC_OPCODE_MOV;
324 switch(inst->U.I.Opcode) {
|
| radeon_pair_schedule.c | 255 else if (sinst->Instruction->U.P.Alpha.Opcode == RC_OPCODE_NOP)
257 else if (sinst->Instruction->U.P.RGB.Opcode == RC_OPCODE_NOP)
456 inst_begin->U.I.Opcode = RC_OPCODE_BEGIN_TEX;
511 assert(dst_full->Alpha.Opcode == RC_OPCODE_NOP);
529 info = rc_get_opcode_info(dst_full->RGB.Opcode);
602 const struct rc_opcode_info * opcode; local
604 assert(rgb->Alpha.Opcode == RC_OPCODE_NOP);
605 assert(alpha->RGB.Opcode == RC_OPCODE_NOP);
625 opcode = rc_get_opcode_info(alpha->Alpha.Opcode);
1316 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.h | 133 virtual bool isPredicated(unsigned Opcode) const;
135 virtual bool isPredicatedTrue(unsigned Opcode) const;
137 virtual bool isPredicatedNew(unsigned Opcode) const;
158 bool isValidOffset(const int Opcode, const int Offset) const;
195 bool isNewValueStore(unsigned Opcode) const;
212 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
213 bool PredOpcodeHasNot(Opcode_t Opcode) const;
|
| /external/llvm/lib/Transforms/Instrumentation/ |
| ProfilingUtils.cpp | 73 Instruction::CastOps opcode = CastInst::getCastOpcode(AI, false, ArgVTy, local
76 CastInst::Create(opcode, AI, ArgVTy, "argv.cast", InitCall));
87 Instruction::CastOps opcode; local
89 opcode = CastInst::getCastOpcode(InitCall, true, AI->getType(), true);
91 CastInst::Create(opcode, InitCall, AI->getType(), "", InsertPos));
93 opcode = CastInst::getCastOpcode(AI, true,
96 CastInst::Create(opcode, AI, Type::getInt32Ty(Context),
|
| /dalvik/libdex/ |
| InstrUtils.cpp | 21 * automatically by the opcode-gen tool. Any edits to the generated
29 * Table that maps each opcode to the full width of instructions that
30 * use that opcode, in (16-bit) code units. Unimplemented opcodes as
31 * well as the "breakpoint" opcode have a width of zero.
34 // BEGIN(libdex-widths); GENERATED AUTOMATICALLY BY opcode-gen
55 * Table that maps each opcode to the flags associated with that
56 * opcode.
59 // BEGIN(libdex-flags); GENERATED AUTOMATICALLY BY opcode-gen
320 * Table that maps each opcode to the instruction format associated
321 * that opcode
493 Opcode opcode = dexOpcodeFromCodeUnit(inst); local
[all...] |
| /external/bluetooth/bluedroid/hci/src/ |
| hci_h4.c | 52 ** 2-bytes for opcode and 1 byte for length
57 ** 1-byte for opcode and 1 byte for length
126 uint16_t opcode; /* OPCODE of outstanding internal commands */ member in struct:__anon732
159 uint8_t hci_h4_send_int_cmd(uint16_t opcode, HC_BT_HDR *p_buf, \
195 uint16_t opcode, len=0; local
199 STREAM_TO_UINT16(opcode, p)
204 if (opcode == HCI_READ_BUFFER_SIZE)
226 else if (opcode == HCI_LE_READ_BUFFER_SIZE)
258 uint16_t opcode, len local
[all...] |
| hci_mct.c | 53 ** 2-bytes for opcode and 1 byte for length
58 ** 1-byte for opcode and 1 byte for length
104 uint16_t opcode; /* OPCODE of outstanding internal commands */ member in struct:__anon735
142 uint8_t hci_mct_send_int_cmd(uint16_t opcode, HC_BT_HDR *p_buf, \
178 uint16_t opcode, len=0; local
182 STREAM_TO_UINT16(opcode, p)
187 if (opcode == HCI_READ_BUFFER_SIZE)
209 else if (opcode == HCI_LE_READ_BUFFER_SIZE)
241 uint16_t opcode, len local
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 326 negativeOffsetOpcode(unsigned opcode)
328 switch (opcode) {
346 return opcode;
356 positiveOffsetOpcode(unsigned opcode)
358 switch (opcode) {
376 return opcode;
386 immediateOffsetOpcode(unsigned opcode)
388 switch (opcode) {
414 return opcode;
426 unsigned Opcode = MI.getOpcode()
[all...] |
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.cpp | 86 // If rows are added to the opcode extension tables, then corresponding entries
100 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
226 Opcode = byteFromRec(Rec, "Opcode");
688 // Operand 1 is added to the opcode.
697 // Operand 2 is a register operand in the Reg/Opcode field.
719 // Operand 2 is a register operand in the Reg/Opcode field.
742 // Operand 1 is a register operand in the Reg/Opcode field.
779 // Operand 1 is a register operand in the Reg/Opcode field.
872 if (Opcode == 0xc6)
[all...] |
| /external/chromium_org/v8/src/mips/ |
| assembler-mips.cc | 487 uint32_t opcode = GetOpcodeField(instr); local
491 return opcode == BEQ ||
492 opcode == BNE ||
493 opcode == BLEZ ||
494 opcode == BGTZ ||
495 opcode == BEQL ||
496 opcode == BNEL ||
497 opcode == BLEZL ||
498 opcode == BGTZL ||
499 (opcode == REGIMM && (rt_field == BLTZ || rt_field == BGEZ |
522 uint32_t opcode = GetOpcodeField(instr); local
534 uint32_t opcode = GetOpcodeField(instr); local
556 uint32_t opcode = GetOpcodeField(instr); local
563 uint32_t opcode = GetOpcodeField(instr); local
[all...] |
| /external/chromium_org/third_party/openssl/openssl/crypto/modes/asm/ |
| ghash-parisc.pl | 639 { my $opcode=(0x03<<26)|($2<<21)|($1<<16)|(3<<6)|$3;
640 sprintf "\t.WORD\t0x%08x\t; %s",$opcode,$orig;
643 { my $opcode=(0x03<<26)|($2<<21)|(1<<12)|(3<<6)|$3;
644 $opcode|=(($1&0xF)<<17)|(($1&0x10)<<12); # encode offset
645 $opcode|=(1<<5) if ($mod =~ /^,m/);
646 $opcode|=(1<<13) if ($mod =~ /^,mb/);
647 sprintf "\t.WORD\t0x%08x\t; %s",$opcode,$orig;
657 { my $opcode=(0x1c<<26)|($3<<21)|($1<<16)|(($2&0x1FF8)<<1)|(($2>>13)&1);
658 sprintf "\t.WORD\t0x%08x\t; %s",$opcode,$orig;
669 { my $opcode=(0x36<<26)|($1<<21)|($4<<16)
[all...] |
| /external/openssl/crypto/modes/asm/ |
| ghash-parisc.pl | 639 { my $opcode=(0x03<<26)|($2<<21)|($1<<16)|(3<<6)|$3;
640 sprintf "\t.WORD\t0x%08x\t; %s",$opcode,$orig;
643 { my $opcode=(0x03<<26)|($2<<21)|(1<<12)|(3<<6)|$3;
644 $opcode|=(($1&0xF)<<17)|(($1&0x10)<<12); # encode offset
645 $opcode|=(1<<5) if ($mod =~ /^,m/);
646 $opcode|=(1<<13) if ($mod =~ /^,mb/);
647 sprintf "\t.WORD\t0x%08x\t; %s",$opcode,$orig;
657 { my $opcode=(0x1c<<26)|($3<<21)|($1<<16)|(($2&0x1FF8)<<1)|(($2>>13)&1);
658 sprintf "\t.WORD\t0x%08x\t; %s",$opcode,$orig;
669 { my $opcode=(0x36<<26)|($1<<21)|($4<<16)
[all...] |
| /dalvik/dx/src/com/android/dx/io/instructions/ |
| DecodedInstruction.java | 28 * numeric opcode, an optional index type, and any additional
43 /** opcode number */
44 private final int opcode; field in class:DecodedInstruction
71 int opcode = Opcodes.extractOpcodeFromUnit(opcodeUnit); local
72 InstructionCodec format = OpcodeInfo.getFormat(opcode);
101 public DecodedInstruction(InstructionCodec format, int opcode,
107 if (!Opcodes.isValidShape(opcode)) {
108 throw new IllegalArgumentException("invalid opcode");
112 this.opcode = opcode;
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/io/instructions/ |
| DecodedInstruction.java | 28 * numeric opcode, an optional index type, and any additional
43 /** opcode number */
44 private final int opcode; field in class:DecodedInstruction
71 int opcode = Opcodes.extractOpcodeFromUnit(opcodeUnit); local
72 InstructionCodec format = OpcodeInfo.getFormat(opcode);
101 public DecodedInstruction(InstructionCodec format, int opcode,
107 if (!Opcodes.isValidShape(opcode)) {
108 throw new IllegalArgumentException("invalid opcode");
112 this.opcode = opcode;
[all...] |
| /external/javassist/src/main/javassist/compiler/ |
| Javac.java | 31 import javassist.bytecode.Opcode;
238 if (op == Opcode.DRETURN)
239 value = Opcode.DCONST_0;
240 else if (op == Opcode.FRETURN)
241 value = Opcode.FCONST_0;
242 else if (op == Opcode.LRETURN)
243 value = Opcode.LCONST_0;
244 else if (op == Opcode.RETURN)
245 value = Opcode.NOP;
247 value = Opcode.ICONST_0
[all...] |
| /external/chromium_org/net/server/ |
| web_socket.cc | 148 typedef int OpCode;
150 const OpCode kOpCodeContinuation = 0x0;
151 const OpCode kOpCodeText = 0x1;
152 const OpCode kOpCodeBinary = 0x2;
153 const OpCode kOpCodeClose = 0x8;
154 const OpCode kOpCodePing = 0x9;
155 const OpCode kOpCodePong = 0xA;
244 OpCode op_code_;
365 OpCode op_code = kOpCodeText;
|
