1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Hexagon implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef HexagonINSTRUCTIONINFO_H 15 #define HexagonINSTRUCTIONINFO_H 16 17 #include "HexagonRegisterInfo.h" 18 #include "MCTargetDesc/HexagonBaseInfo.h" 19 #include "llvm/Target/TargetInstrInfo.h" 20 #include "llvm/Target/TargetFrameLowering.h" 21 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" 22 23 #define GET_INSTRINFO_HEADER 24 #include "HexagonGenInstrInfo.inc" 25 26 namespace llvm { 27 28 class HexagonInstrInfo : public HexagonGenInstrInfo { 29 const HexagonRegisterInfo RI; 30 const HexagonSubtarget &Subtarget; 31 typedef unsigned Opcode_t; 32 33 public: 34 explicit HexagonInstrInfo(HexagonSubtarget &ST); 35 36 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 37 /// such, whenever a client has an instance of instruction info, it should 38 /// always be able to get register info as well (through this method). 39 /// 40 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; } 41 42 /// isLoadFromStackSlot - If the specified machine instruction is a direct 43 /// load from a stack slot, return the virtual or physical register number of 44 /// the destination along with the FrameIndex of the loaded stack slot. If 45 /// not, return 0. This predicate must return 0 if the instruction has 46 /// any side effects other than loading from the stack slot. 47 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 48 int &FrameIndex) const; 49 50 /// isStoreToStackSlot - If the specified machine instruction is a direct 51 /// store to a stack slot, return the virtual or physical register number of 52 /// the source reg along with the FrameIndex of the loaded stack slot. If 53 /// not, return 0. This predicate must return 0 if the instruction has 54 /// any side effects other than storing to the stack slot. 55 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 56 int &FrameIndex) const; 57 58 59 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 60 MachineBasicBlock *&FBB, 61 SmallVectorImpl<MachineOperand> &Cond, 62 bool AllowModify) const; 63 64 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 65 66 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 67 MachineBasicBlock *FBB, 68 const SmallVectorImpl<MachineOperand> &Cond, 69 DebugLoc DL) const; 70 71 virtual bool analyzeCompare(const MachineInstr *MI, 72 unsigned &SrcReg, unsigned &SrcReg2, 73 int &Mask, int &Value) const; 74 75 virtual void copyPhysReg(MachineBasicBlock &MBB, 76 MachineBasicBlock::iterator I, DebugLoc DL, 77 unsigned DestReg, unsigned SrcReg, 78 bool KillSrc) const; 79 80 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 81 MachineBasicBlock::iterator MBBI, 82 unsigned SrcReg, bool isKill, int FrameIndex, 83 const TargetRegisterClass *RC, 84 const TargetRegisterInfo *TRI) const; 85 86 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 87 SmallVectorImpl<MachineOperand> &Addr, 88 const TargetRegisterClass *RC, 89 SmallVectorImpl<MachineInstr*> &NewMIs) const; 90 91 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 92 MachineBasicBlock::iterator MBBI, 93 unsigned DestReg, int FrameIndex, 94 const TargetRegisterClass *RC, 95 const TargetRegisterInfo *TRI) const; 96 97 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 98 SmallVectorImpl<MachineOperand> &Addr, 99 const TargetRegisterClass *RC, 100 SmallVectorImpl<MachineInstr*> &NewMIs) const; 101 102 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 103 MachineInstr* MI, 104 const SmallVectorImpl<unsigned> &Ops, 105 int FrameIndex) const; 106 107 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 108 MachineInstr* MI, 109 const SmallVectorImpl<unsigned> &Ops, 110 MachineInstr* LoadMI) const { 111 return 0; 112 } 113 114 unsigned createVR(MachineFunction* MF, MVT VT) const; 115 116 virtual bool isBranch(const MachineInstr *MI) const; 117 virtual bool isPredicable(MachineInstr *MI) const; 118 virtual bool 119 PredicateInstruction(MachineInstr *MI, 120 const SmallVectorImpl<MachineOperand> &Cond) const; 121 122 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 123 unsigned ExtraPredCycles, 124 const BranchProbability &Probability) const; 125 126 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 127 unsigned NumTCycles, unsigned ExtraTCycles, 128 MachineBasicBlock &FMBB, 129 unsigned NumFCycles, unsigned ExtraFCycles, 130 const BranchProbability &Probability) const; 131 132 virtual bool isPredicated(const MachineInstr *MI) const; 133 virtual bool isPredicated(unsigned Opcode) const; 134 virtual bool isPredicatedTrue(const MachineInstr *MI) const; 135 virtual bool isPredicatedTrue(unsigned Opcode) const; 136 virtual bool isPredicatedNew(const MachineInstr *MI) const; 137 virtual bool isPredicatedNew(unsigned Opcode) const; 138 virtual bool DefinesPredicate(MachineInstr *MI, 139 std::vector<MachineOperand> &Pred) const; 140 virtual bool 141 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 142 const SmallVectorImpl<MachineOperand> &Pred2) const; 143 144 virtual bool 145 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 146 147 virtual bool 148 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles, 149 const BranchProbability &Probability) const; 150 151 virtual DFAPacketizer* 152 CreateTargetScheduleState(const TargetMachine *TM, 153 const ScheduleDAG *DAG) const; 154 155 virtual bool isSchedulingBoundary(const MachineInstr *MI, 156 const MachineBasicBlock *MBB, 157 const MachineFunction &MF) const; 158 bool isValidOffset(const int Opcode, const int Offset) const; 159 bool isValidAutoIncImm(const EVT VT, const int Offset) const; 160 bool isMemOp(const MachineInstr *MI) const; 161 bool isSpillPredRegOp(const MachineInstr *MI) const; 162 bool isU6_3Immediate(const int value) const; 163 bool isU6_2Immediate(const int value) const; 164 bool isU6_1Immediate(const int value) const; 165 bool isU6_0Immediate(const int value) const; 166 bool isS4_3Immediate(const int value) const; 167 bool isS4_2Immediate(const int value) const; 168 bool isS4_1Immediate(const int value) const; 169 bool isS4_0Immediate(const int value) const; 170 bool isS12_Immediate(const int value) const; 171 bool isU6_Immediate(const int value) const; 172 bool isS8_Immediate(const int value) const; 173 bool isS6_Immediate(const int value) const; 174 175 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const; 176 bool isConditionalTransfer(const MachineInstr* MI) const; 177 bool isConditionalALU32 (const MachineInstr* MI) const; 178 bool isConditionalLoad (const MachineInstr* MI) const; 179 bool isConditionalStore(const MachineInstr* MI) const; 180 bool isNewValueInst(const MachineInstr* MI) const; 181 bool isNewValue(const MachineInstr* MI) const; 182 bool isDotNewInst(const MachineInstr* MI) const; 183 int GetDotOldOp(const int opc) const; 184 int GetDotNewOp(const MachineInstr* MI) const; 185 int GetDotNewPredOp(MachineInstr *MI, 186 const MachineBranchProbabilityInfo 187 *MBPI) const; 188 bool mayBeNewStore(const MachineInstr* MI) const; 189 bool isDeallocRet(const MachineInstr *MI) const; 190 unsigned getInvertedPredicatedOpcode(const int Opc) const; 191 bool isExtendable(const MachineInstr* MI) const; 192 bool isExtended(const MachineInstr* MI) const; 193 bool isPostIncrement(const MachineInstr* MI) const; 194 bool isNewValueStore(const MachineInstr* MI) const; 195 bool isNewValueStore(unsigned Opcode) const; 196 bool isNewValueJump(const MachineInstr* MI) const; 197 bool isNewValueJumpCandidate(const MachineInstr *MI) const; 198 199 200 void immediateExtend(MachineInstr *MI) const; 201 bool isConstExtended(MachineInstr *MI) const; 202 int getDotNewPredJumpOp(MachineInstr *MI, 203 const MachineBranchProbabilityInfo *MBPI) const; 204 unsigned getAddrMode(const MachineInstr* MI) const; 205 bool isOperandExtended(const MachineInstr *MI, 206 unsigned short OperandNum) const; 207 unsigned short getCExtOpNum(const MachineInstr *MI) const; 208 int getMinValue(const MachineInstr *MI) const; 209 int getMaxValue(const MachineInstr *MI) const; 210 bool NonExtEquivalentExists (const MachineInstr *MI) const; 211 short getNonExtOpcode(const MachineInstr *MI) const; 212 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const; 213 bool PredOpcodeHasNot(Opcode_t Opcode) const; 214 215 private: 216 int getMatchingCondBranchOpcode(int Opc, bool sense) const; 217 218 }; 219 220 } 221 222 #endif 223
