| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIGenRegisterInfo.pl | 47 class SI_64 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
52 class SI_128 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
57 class SI_256 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
75 class SGPR_64 <bits<8> num, string name, list<Register> subregs> :
76 SI_64 <name, subregs>;
78 class VGPR_64 <bits<9> num, string name, list<Register> subregs> :
79 SI_64 <name, subregs>;
[all...] |
| R600GenRegisterInfo.pl | 31 class R600Reg_128<string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIGenRegisterInfo.pl | 47 class SI_64 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
52 class SI_128 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
57 class SI_256 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
75 class SGPR_64 <bits<8> num, string name, list<Register> subregs> :
76 SI_64 <name, subregs>;
78 class VGPR_64 <bits<9> num, string name, list<Register> subregs> :
79 SI_64 <name, subregs>;
[all...] |
| R600GenRegisterInfo.pl | 31 class R600Reg_128<string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
|
| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
198 unsigned SubReg = *SubRegs;
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
221 SubRegs.isValid(); ++SubRegs)
222 PartDefRegs.insert(*SubRegs);
251 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
[all...] |
| PostRASchedulerList.cpp | 427 // Repeat, for reg and all subregs.
428 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
429 SubRegs.isValid(); ++SubRegs)
430 LiveRegs.set(*SubRegs);
455 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) {
456 if (LiveRegs.test(*SubRegs)) {
457 MIB.addReg(*SubRegs, RegState::ImplicitDefine)
[all...] |
| RegisterScavenging.cpp | 34 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
35 SubRegs.isValid(); ++SubRegs)
36 RegsAvailable.reset(*SubRegs);
107 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
108 SubRegs.isValid(); ++SubRegs)
109 BV.set(*SubRegs);
220 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs
[all...] |
| MachineInstrBundle.cpp | 174 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
175 unsigned SubReg = *SubRegs;
|
| IfConversion.cpp | [all...] |
| CriticalAntiDepBreaker.cpp | 204 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
205 SubRegs.isValid(); ++SubRegs)
206 KeepRegs.set(*SubRegs);
249 // Repeat, for all subregs.
250 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
251 unsigned SubregReg = *SubRegs;
|
| MachineVerifier.cpp | 95 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
96 RV.push_back(*SubRegs);
453 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
455 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
456 regsReserved.set(*SubRegs);
676 for (MCSubRegIterator SubRegs(*I, TRI, /*IncludeSelf=*/true)
[all...] |
| AggressiveAntiDepBreaker.cpp | 250 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
251 SubRegs.isValid(); ++SubRegs)
252 PassthruRegs.insert(*SubRegs);
317 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
318 unsigned SubregReg = *SubRegs;
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.td | 20 class HexagonDoubleReg<string n, list<Register> subregs> :
21 RegisterWithSubRegs<n, subregs> {
38 class Rd<bits<5> num, string n, list<Register> subregs> :
39 HexagonDoubleReg<n, subregs> {
41 let SubRegs = subregs;
|
| /external/llvm/lib/Target/R600/ |
| R600RegisterInfo.td | 19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
20 RegisterWithSubRegs<n, subregs> {
26 class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :
27 RegisterWithSubRegs<n, subregs> {
212 class IndirectSuper<string n, list<Register> subregs> :
213 RegisterWithSubRegs<n, subregs> {
|
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.td | 36 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
37 : RegisterWithSubRegs<n, subregs> {
46 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
47 : MipsRegWithSubRegs<Enc, n, subregs> {
55 class AFPR<bits<16> Enc, string n, list<Register> subregs>
56 : MipsRegWithSubRegs<Enc, n, subregs> {
61 class AFPR64<bits<16> Enc, string n, list<Register> subregs>
62 : MipsRegWithSubRegs<Enc, n, subregs> {
67 class ACC<bits<16> Enc, string n, list<Register> subregs>
68 : MipsRegWithSubRegs<Enc, n, subregs> {
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
123 "SubRegs and SubRegIndices must have the same size");
131 // covered-by-subregs super-registers where it appears as the first explicit
213 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
226 return SubRegs;
229 // First insert the explicit subregs and make sure they are fully indexed.
233 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
241 // Keep track of inherited subregs and how they can be reached.
244 // Clone inherited subregs and place duplicate entries in Orphans
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.td | 36 let SubRegs = [SubReg];
56 class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
58 let SubRegs = subregs;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.td | 19 class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs>
20 : RegisterWithSubRegs<n, subregs> {
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.td | 32 class AArch64RegWithSubs<bits<16> enc, string n, list<Register> subregs = [],
35 let SubRegs = subregs;
|
| AArch64MCInstLower.cpp | 106 assert(!MO.getSubReg() && "Subregs should be eliminated!");
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.td | 38 class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
40 let SubRegs = subregs;
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.td | 18 class SystemZRegWithSubregs<string n, list<Register> subregs>
19 : RegisterWithSubRegs<n, subregs> {
100 // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
|
| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.td | 15 class ARMReg<bits<16> Enc, string n, list<Register> subregs = []> : Register<n> {
18 let SubRegs = subregs;
291 // 32-bit SPR subregs).
308 // Subset of QPR that have 32-bit SPR subregs.
312 // Subset of QPR that have DPR_8 and SPR_8 subregs.
|
| /external/llvm/include/llvm/Target/ |
| Target.td | 48 // in the SubRegs field of a Register definition. For example:
90 // SubRegs - A list of registers that are parts of this register. Note these
92 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
94 list<Register> SubRegs = [];
96 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
98 // SubRegs.
132 // List "subregs" specifies which registers are sub-registers to this one. This
133 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
136 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
137 let SubRegs = subregs
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 103 /// register. The SubRegs field is a zero terminated array of registers that
111 uint32_t SubRegs; // Sub-register set, described above
115 // sub-register in SubRegs.
445 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
|
