| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.cpp | 48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
|
| ARMFastISel.cpp | 299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
310 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
313 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
315 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
330 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
334 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
337 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
353 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
358 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
362 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL
[all...] |
| Thumb2InstrInfo.cpp | 121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
144 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
157 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
186 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
228 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
234 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
243 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
249 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
264 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg
[all...] |
| Thumb1FrameLowering.cpp | 174 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
206 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
287 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
291 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
315 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
321 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
344 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
383 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
|
| ARMFrameLowering.cpp | 225 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
298 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
309 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
311 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
315 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
329 BuildMI(MBB, MBBI, dl,
334 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
410 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
417 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
420 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr)
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ControlFlowFinalizer.cpp | 167 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead),
207 InsertPos = BuildMI(MBB, InsertPos->getDebugLoc(),
252 MachineInstr *MILit = BuildMI(MBB, I, I->getDebugLoc(),
269 BuildMI(BB, InsertPos->getDebugLoc(), TII->get(AMDGPU::FETCH_CLAUSE))
283 BuildMI(BB, InsertPos->getDebugLoc(), TII->get(AMDGPU::ALU_CLAUSE))
344 BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
391 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
408 BuildMI(MBB, MI, MBB.findDebugLoc(MI), getHWInstrDesc(CF_END_LOOP))
416 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI),
430 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 122 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
125 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::CONST32_Int_Real),
127 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::SUB_rr),
132 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
161 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME));
162 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::ADD_rr),
183 BuildMI(MBB, MBBI_end, dl, TII.get(Hexagon::DEALLOC_RET_V4));
198 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME));
|
| HexagonCopyToCombine.cpp | 567 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ii), DoubleDestReg)
574 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_iI_V4), DoubleDestReg)
584 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ii), DoubleDestReg)
592 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_iI_V4), DoubleDestReg)
600 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ii), DoubleDestReg)
617 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ir_V4), DoubleDestReg)
625 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ir_V4), DoubleDestReg)
642 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rI_V4), DoubleDestReg)
651 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rI_V4), DoubleDestReg)
670 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rr), DoubleDestReg
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 51 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
55 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
79 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
82 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
100 BuildMI(MBB, I, DL, get(Opc), DestReg)
272 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
278 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
283 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
|
| MSP430BranchSelector.cpp | 155 BuildMI(MBB, I, dl, TII->get(MSP430::JCC))
161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 286 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
290 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
294 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
311 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
316 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
322 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
326 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
336 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
341 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
347 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1
[all...] |
| PPCInstrInfo.cpp | 195 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
219 BuildMI(MBB, MI, DL, get(PPC::NOP));
403 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
405 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
409 BuildMI(&MBB, DL, get(PPC::BCC))
416 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
420 BuildMI(&MBB, DL, get(PPC::BCC))
422 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
521 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
525 BuildMI(MBB, MI, dl, get(OpCode), DestReg
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 232 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
575 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
653 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
657 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
674 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
679 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
683 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
687 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
692 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, IsIndirect,
804 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 82 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
97 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
112 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
145 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WAITCNT))
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
164 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp)
170 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32))
191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
194 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_MOV_F32))
207 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMPX_LE_F32_e32)
[all...] |
| SIInstrInfo.cpp | 48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 82 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
97 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
112 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
145 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WAITCNT))
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
164 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp)
170 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32))
191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
194 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_MOV_F32))
207 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMPX_LE_F32_e32)
[all...] |
| SIInstrInfo.cpp | 48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 51 BuildMI(MBB, MI, DL, get(Mips::NOP));
100 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
132 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
139 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
281 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
|
| MipsSEInstrInfo.cpp | 113 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
132 BuildMI(MBB, I, DL, get(Mips::WRDSP))
165 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
208 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
241 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
323 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
326 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
358 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
360 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
365 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill
[all...] |
| Mips16FrameLowering.cpp | 51 BuildMI(MBB, MBBI, dl,
57 BuildMI(MBB, MBBI, dl,
72 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
90 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
|
| Mips16ISelLowering.cpp | 524 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
540 BuildMI(*BB, BB->begin(), DL,
587 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
589 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
604 BuildMI(*BB, BB->begin(), DL,
652 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
654 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
669 BuildMI(*BB, BB->begin(), DL,
689 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
691 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target)
[all...] |
| MipsSEFrameLowering.cpp | 128 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
147 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
176 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
178 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
204 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR0).addReg(Lo, SrcKill);
206 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR1).addReg(Hi, SrcKill);
244 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR0).addReg(SrcLo, SrcKill);
245 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
247 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR1).addReg(SrcHi, SrcKill);
248 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi
[all...] |
| Mips16ISelDAGToDAG.cpp | 83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
85 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
87 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
88 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
107 BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg)
|
| /external/llvm/lib/CodeGen/ |
| ErlangGC.cpp | 58 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
|
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 228 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
248 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
288 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
317 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
573 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg);
818 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
835 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
842 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
922 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc))
934 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareOpc)
[all...] |
