| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 291 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
343 if (N->getOpcode() != ISD::ADD)
358 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
359 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
385 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
404 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
407 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
409 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
433 if (Use->getOpcode() == ISD::CopyToReg)
533 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &
[all...] |
| ARMCallingConv.h | 60 ISD::ArgFlagsTy &ArgFlags,
114 ISD::ArgFlagsTy &ArgFlags,
146 ISD::ArgFlagsTy &ArgFlags,
157 ISD::ArgFlagsTy &ArgFlags,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 88 case ISD::TokenFactor: break;
89 case ISD::CopyFromReg: NumberDeps++; break;
90 case ISD::CopyToReg: break;
91 case ISD::INLINEASM: break;
125 case ISD::TokenFactor: break;
126 case ISD::CopyFromReg: break;
127 case ISD::CopyToReg: NumberDeps++; break;
128 case ISD::INLINEASM: break;
457 case ISD::TokenFactor:
458 case ISD::CopyFromReg
[all...] |
| SelectionDAGISel.cpp | 556 if (N->getOpcode() != ISD::CopyToReg)
796 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
[all...] |
| InstrEmitter.cpp | 113 if (User->getOpcode() == ISD::CopyToReg &&
196 if (User->getOpcode() == ISD::CopyToReg &&
233 if (User->getOpcode() == ISD::CopyToReg &&
336 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
461 if (User->getOpcode() == ISD::CopyToReg &&
800 if (F->getOpcode() == ISD::CopyFromReg) {
803 } else if (F->getOpcode() == ISD::CopyToReg)
[all...] |
| LegalizeTypes.cpp | [all...] |
| ScheduleDAGSDNodes.h | 68 if (Node->getOpcode() == ISD::EntryToken ||
|
| ScheduleDAGSDNodes.cpp | 114 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
389 if (NI->getOpcode() == ISD::TokenFactor)
411 if (SUNode->getOpcode() != ISD::CopyToReg)
485 if(isChain && OpN->getOpcode() == ISD::TokenFactor)
532 if (Node->getOpcode() == ISD::CopyFromReg)
591 if (N && N->getOpcode() == ISD::TokenFactor) {
633 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
[all...] |
| ScheduleDAGRRList.cpp | 288 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) {
416 if (N->getOpcode() == ISD::TokenFactor) {
442 if (N->getOpcode() == ISD::EntryToken)
463 if (N->getOpcode() == ISD::TokenFactor) {
502 if (N->getOpcode() == ISD::EntryToken)
676 case ISD::MERGE_VALUES:
677 case ISD::TokenFactor:
678 case ISD::LIFETIME_START:
679 case ISD::LIFETIME_END:
680 case ISD::CopyToReg
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 95 if (Addr.getOpcode() == ISD::ADD) {
113 case ISD::Constant: {
173 case ISD::BRIND:
191 if (Chain->getOpcode() != ISD::TokenFactor)
205 return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
214 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
245 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelDAGToDAG.cpp | 112 if (Addr.getOpcode() == ISD::FrameIndex) {
120 } else if (Addr.getOpcode() == ISD::ADD) {
131 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
132 Addr.getOpcode() == ISD::TargetGlobalAddress) {
140 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
141 Addr.getOpcode() == ISD::TargetGlobalAddress) {
145 if (Addr.getOpcode() == ISD::FrameIndex) {
153 } else if (Addr.getOpcode() == ISD::ADD) {
258 case ISD::BUILD_VECTOR: {
294 case ISD::BUILD_PAIR:
[all...] |
| AMDGPUISelLowering.h | 47 const SmallVectorImpl<ISD::InputArg> &Ins) const;
57 const SmallVectorImpl<ISD::OutputArg> &Outs,
117 // AMDIL ISD Opcodes
118 FIRST_NUMBER = ISD::BUILTIN_OP_END,
124 // End AMDIL ISD Opcodes
|
| R600ISelLowering.h | 38 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| SIISelLowering.h | 50 const SmallVectorImpl<ISD::InputArg> &Ins,
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 46 const SmallVectorImpl<ISD::InputArg> &Ins,
52 const SmallVectorImpl<ISD::OutputArg> &Outs,
105 // AMDIL ISD Opcodes
106 FIRST_NUMBER = ISD::BUILTIN_OP_END,
114 // End AMDIL ISD Opcodes
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVarargsCallingConvention.h | 22 ISD::ArgFlagsTy ArgFlags,
31 ISD::ArgFlagsTy ArgFlags,
100 ISD::ArgFlagsTy ArgFlags,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 256 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
257 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
258 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
259 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
260 case Intrinsic::rint: Opcode = ISD::FRINT; break;
261 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
287 continue; // ISD::FCOPYSIGN is never a library call.
291 continue; // ISD::FABS is never a library call.
295 Opcode = ISD::FSQRT; break;
299 Opcode = ISD::FFLOOR; break
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
383 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
595 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
793 const SmallVectorImpl<ISD::InputArg> &Ins,
798 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
805 ISD::ArgFlagsTy Flags) const;
818 const SmallVectorImpl<ISD::OutputArg> &Outs,
820 const SmallVectorImpl<ISD::InputArg> &Ins,
[all...] |
| X86SelectionDAGInfo.cpp | 150 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
166 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
258 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
260 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
268 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 46 const SmallVectorImpl<ISD::InputArg> &Ins,
52 const SmallVectorImpl<ISD::OutputArg> &Outs,
105 // AMDIL ISD Opcodes
106 FIRST_NUMBER = ISD::BUILTIN_OP_END,
114 // End AMDIL ISD Opcodes
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 221 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
222 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
257 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
258 Addr.getOpcode() == ISD::TargetGlobalAddress))
280 if (Addr.getOpcode() == ISD::ADD) {
330 case ISD::SUBE: {
336 case ISD::ADDE: {
344 case ISD::ConstantFP:
[all...] |
| Mips16ISelLowering.cpp | 133 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
134 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
135 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
136 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
137 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
138 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
139 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
140 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
141 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
142 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
67 // Wrappers around the ISD opcodes of the same name. The output and
93 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
160 const SmallVectorImpl<ISD::InputArg> &Ins,
170 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/MC/ |
| MCMachOStreamer.cpp | 227 IndirectSymbolData ISD;
228 ISD.Symbol = Symbol;
229 ISD.SectionData = getCurrentSectionData();
230 getAssembler().getIndirectSymbols().push_back(ISD);
|
| /external/clang/test/CXX/temp/temp.spec/temp.expl.spec/ |
| examples.cpp | 232 namespace ISD {
234 template class BasicStringPiece<int>; // expected-error {{explicit instantiation of undefined template 'spec_vs_expl_inst::ISD::BasicStringPiece<int>'}}
|
