| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 24 #include "llvm/MC/MCInst.h"
53 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
61 void EmitALUInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
63 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
64 void EmitDst(const MCInst &MI, raw_ostream &OS) const;
65 void EmitALU(const MCInst &MI, unsigned numSrc,
68 void EmitTexInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
70 void EmitFCInstr(const MCInst &MI, raw_ostream &OS) const;
87 bool isFlagSet(const MCInst &MI, unsigned Operand, unsigned Flag) const
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCAtom.h | 19 #include "llvm/MC/MCInst.h"
113 MCInst Inst;
116 MCDecodedInst(const MCInst &Inst, uint64_t Address, uint64_t Size)
131 void addInst(const MCInst &Inst, uint64_t Size);
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| MCELFStreamer.h | 25 class MCInst;
96 virtual void EmitInstToFragment(const MCInst &Inst);
97 virtual void EmitInstToData(const MCInst &Inst);
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| MCObjectStreamer.h | 38 virtual void EmitInstToData(const MCInst &Inst) = 0;
87 virtual void EmitInstruction(const MCInst &Inst);
91 virtual void EmitInstToFragment(const MCInst &Inst);
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| MCInstPrinter.h | 1 //===-- MCInstPrinter.h - Convert an MCInst to target assembly syntax -----===//
17 class MCInst;
32 /// that converts an MCInst to valid target assembly syntax.
68 /// printInst - Print the specified MCInst to the specified raw_ostream.
70 virtual void printInst(const MCInst *MI, raw_ostream &OS,
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| MCTargetAsmParser.h | 21 class MCInst;
119 /// construct the appropriate MCInst, or emit an error. On success, the entire
149 /// instruction as an actual MCInst and emit it to the specified MCStreamer.
171 virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {
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| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.h | 31 void getNoopForMachoTarget(MCInst &NopInst) const;
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 22 #include "llvm/MC/MCInst.h"
47 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
51 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
90 void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
170 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
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| SIMCCodeEmitter.cpp | 21 #include "llvm/MC/MCInst.h"
57 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
61 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
127 void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
169 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 10 // Print MCInst instructions to .ptx format.
19 #include "llvm/MC/MCInst.h"
72 void NVPTXInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
80 void NVPTXInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
94 void NVPTXInstPrinter::printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O,
144 void NVPTXInstPrinter::printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O,
217 void NVPTXInstPrinter::printLdStCode(const MCInst *MI, int OpNum,
265 void NVPTXInstPrinter::printMemOperand(const MCInst *MI, int OpNum,
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 10 // This file includes code for rendering MCInst instances as AT&T-style
22 #include "llvm/MC/MCInst.h"
42 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
62 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
86 void X86ATTInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
130 void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
151 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
173 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
15 #include "llvm/MC/MCInst.h"
208 void ProcessInstruction(MCInst &Inst,
385 void addRegOperands(MCInst &Inst, unsigned N) const {
389 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
394 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
399 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
404 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
409 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
416 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
15 #include "llvm/MC/MCInst.h"
131 bool needsExpansion(MCInst &Inst);
133 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
134 SmallVectorImpl<MCInst> &Instructions);
135 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
136 SmallVectorImpl<MCInst> &Instructions);
137 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
138 SmallVectorImpl<MCInst> &Instructions);
139 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 125 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
132 virtual bool isConditionalBranch(const MCInst &Inst) const {
139 bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
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| AArch64ELFStreamer.cpp | 27 #include "llvm/MC/MCInst.h"
80 virtual void EmitInstruction(const MCInst& Inst) {
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsAsmBackend.cpp | 209 bool mayNeedRelaxation(const MCInst &Inst) const {
230 void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCAsmBackend.cpp | 128 bool mayNeedRelaxation(const MCInst &Inst) const {
142 void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
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| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 22 #include "llvm/MC/MCInst.h"
71 static bool translateInstruction(MCInst &target,
115 X86GenericDisassembler::getInstruction(MCInst &instr,
154 /// register, and appends it as an operand to an MCInst.
156 /// @param mcInst - The MCInst to append to.
158 static void translateRegister(MCInst &mcInst, Reg reg) {
167 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
171 /// immediate Value in the MCInst.
[all...] |
| /external/llvm/lib/MC/ |
| MCDisassembler.cpp | 36 bool MCDisassembler::tryAddingSymbolicOperand(MCInst &Inst, int64_t Value,
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| MCPureStreamer.cpp | 26 virtual void EmitInstToFragment(const MCInst &Inst);
27 virtual void EmitInstToData(const MCInst &Inst);
193 void MCPureStreamer::EmitInstToFragment(const MCInst &Inst) {
200 // able to get away with not storing any extra data in the MCInst.
211 void MCPureStreamer::EmitInstToData(const MCInst &Inst) {
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| Android.mk | 22 MCInst.cpp \
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
25 #include "llvm/MC/MCInst.h"
222 void cvtThumbMultiply(MCInst &Inst,
224 bool validateInstruction(MCInst &Inst,
226 bool processInstruction(MCInst &Inst,
232 bool isDeprecated(MCInst &Inst, StringRef &Info);
274 unsigned checkTargetMatchPredicate(MCInst &Inst);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
11 // MCInst records.
24 #include "llvm/MC/MCInst.h"
34 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
46 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
229 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
237 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
252 Inst = MCInst();
259 static void SimplifyMOVSX(MCInst &Inst) {
280 Inst = MCInst();
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 1 //==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
24 #include "llvm/MC/MCInst.h"
129 bool validateInstruction(MCInst &Inst,
828 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
837 void addBFILSBOperands(MCInst &Inst, unsigned N) const {
844 void addBFIWidthOperands(MCInst &Inst, unsigned N) const {
850 void addBFXWidthOperands(MCInst &Inst, unsigned N) const {
859 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
864 void addCVTFixedPosOperands(MCInst &Inst, unsigned N) const {
871 void addFMOVImmOperands(MCInst &Inst, unsigned N) const
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86AsmBackend.cpp | 112 bool mayNeedRelaxation(const MCInst &Inst) const;
119 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
226 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
266 void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
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