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    Searched refs:MVT (Results 126 - 150 of 153) sorted by null

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  /external/llvm/utils/TableGen/
CodeGenRegisters.h 276 SmallVector<MVT::SimpleValueType, 4> VTs;
289 ArrayRef<MVT::SimpleValueType> getValueTypes() const {return VTs;}
292 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
CodeGenInstruction.cpp 343 /// MVT::Other.
344 MVT::SimpleValueType CodeGenInstruction::
346 if (ImplicitDefs.empty()) return MVT::Other;
351 const std::vector<MVT::SimpleValueType> &RegVTs =
355 return MVT::Other;
501 // If both are Operands with the same MVT, allow the conversion. It's
CodeGenInstruction.h 264 /// MVT::Other.
265 MVT::SimpleValueType
RegisterInfoEmitter.cpp 550 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCTargetTransformInfo.cpp 225 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
PPCCTRLoops.cpp 318 MVT VTy =
320 if (VTy == MVT::Other)
  /external/llvm/lib/Target/R600/
AMDGPUISelLowering.h 54 virtual MVT getVectorIdxTy() const;
  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGFast.cpp 224 if (VT == MVT::Glue)
226 else if (VT == MVT::Other)
232 if (VT == MVT::Glue)
488 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
681 if (NumLeft == NumOps && Op.getValueType() == MVT::Glue) {
729 if (NumVals && N->getValueType(NumVals-1) == MVT::Glue &&
DAGCombiner.cpp     [all...]
ScheduleDAGRRList.cpp 272 /// but for untyped values (MVT::Untyped) it means inspecting the node's
280 MVT VT = RegDefPos.GetValue();
284 if (VT == MVT::Untyped) {
436 if (N->getOperand(i).getValueType() == MVT::Other) {
496 if (N->getOperand(i).getValueType() == MVT::Other) {
    [all...]
LegalizeVectorTypes.cpp 273 Cond, DAG.getValueType(MVT::i1));
310 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
337 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
835 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
    [all...]
LegalizeTypesGeneric.cpp 273 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
463 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
492 assert(Cond.getValueType().getVectorElementType() == MVT::i1 &&
495 EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2);
FunctionLoweringInfo.cpp 211 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
232 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
SelectionDAGBuilder.h 265 unsigned Rg, MVT RgVT, bool E,
274 MVT RegVT;
SelectionDAGDumper.cpp 337 if (getValueType(i) == MVT::Other)
607 if (N->getOperand(i).getValueType() == MVT::Other)
LegalizeTypes.h 126 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
    [all...]
  /external/llvm/lib/Target/X86/
X86RegisterInfo.cpp 524 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
528 case MVT::i8:
531 default: return getX86SubSuperRegister(Reg, MVT::i64);
586 case MVT::i16:
622 case MVT::i32:
658 case MVT::i64:
X86InstrInfo.cpp     [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 561 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
565 if (VT == MVT::i1) {
567 } else if (VT == MVT::i32 || VT == MVT::f32) {
569 } else if (VT == MVT::i64 || VT == MVT::f64) {
    [all...]
HexagonInstrInfo.h 114 unsigned createVR(MachineFunction* MF, MVT VT) const;
  /external/llvm/lib/CodeGen/
TargetRegisterInfo.cpp 111 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
MachineLICM.cpp 783 MVT VT = *RC->vt_begin();
784 if (VT == MVT::Untyped) {
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64ISelLowering.h 271 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
AMDILCFGStructurizer.cpp     [all...]
  /external/mesa3d/src/gallium/drivers/radeon/
AMDILCFGStructurizer.cpp     [all...]

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