| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsFixupKinds.h | 1 //===-- MipsFixupKinds.h - Mips Specific Fixup Entries ----------*- C++ -*-===//
16 namespace Mips {
22 // MCFixupKindInfo Infos[Mips::NumTargetFixupKinds]
135 } // namespace Mips
|
| MipsBaseInfo.h | 1 //===-- MipsBaseInfo.h - Top level definitions for MIPS MC ------*- C++ -*-===//
11 // the Mips target useful for the compiler back-end and the MC libraries.
32 // Mips Specific MachineOperand flags.
99 // Mips instructions.
129 (FixupKind >= MCFixupKind(Mips::LastTargetFixupKind)))
|
| MipsMCTargetDesc.cpp | 1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
10 // This file provides Mips specific target descriptions.
43 // Let's see if there is a dash, like mips-unknown-linux.
54 if (TheTriple == "mips" || TheTriple == "mipsel") {
78 InitMipsMCRegisterInfo(X, Mips::RA);
99 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
|
| /frameworks/compile/mclinker/ |
| Android.mk | 27 # MIPS Code Generation Libraries
29 lib/Target/Mips \
30 lib/Target/Mips/TargetInfo
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.h | 41 return Subtarget->hasDSP() ? &Mips::ACRegsDSPRegClass :
42 &Mips::ACRegsRegClass;
|
| MipsJITInfo.cpp | 1 //===-- MipsJITInfo.cpp - Implement the Mips JIT Interface ----------------===//
10 // This file implements the JIT interfaces for the Mips target.
152 #else // host != Mips
155 "Cannot call MipsCompilationCallback() on a non-Mips arch!");
254 switch ((Mips::RelocationType) MR->getRelocationType()) {
255 case Mips::reloc_mips_pc16:
260 case Mips::reloc_mips_26:
265 case Mips::reloc_mips_hi:
273 case Mips::reloc_mips_lo: {
|
| MipsSEISelLowering.cpp | 25 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26 cl::desc("MIPS: Enable tail calls."), cl::init(false));
34 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
37 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
43 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
81 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
86 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
88 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
221 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
227 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32)
[all...] |
| MipsSubtarget.cpp | 1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
14 #define DEBUG_TYPE "mips-subtarget"
19 #include "Mips.h"
38 "mips-mixed-16-32",
45 "mips-os16",
48 "floating point as Mips 16"),
53 cl::desc("MIPS: mips16 hard float enable."),
107 &Mips::GPR64RegClass : &Mips::GPR32RegClass)
[all...] |
| MipsAsmPrinter.cpp | 1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
15 #define DEBUG_TYPE "mips-asm-printer"
19 #include "Mips.h"
100 // Mips Asm Directives
144 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
145 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
146 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
154 if (Mips::GPR32RegClass.contains(Reg))
158 if (Mips::AFGR64RegClass.contains(Reg))
[all...] |
| MipsInstrInfo.cpp | 1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
31 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
51 BuildMI(MBB, MI, DL, get(Mips::NOP));
127 "# of Mips branch conditions must be <= 3!");
175 "Invalid Mips branch condition!");
|
| MipsDelaySlotFiller.cpp | 1 //===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===//
16 #include "Mips.h"
40 "disable-mips-delay-filler",
46 "disable-mips-df-forward-search",
48 cl::desc("Disallow MIPS delay filler to search forward."),
52 "disable-mips-df-succbb-search",
54 cl::desc("Disallow MIPS delay filler to search successor basic blocks."),
58 "disable-mips-df-backward-search",
60 cl::desc("Disallow MIPS delay filler to search backward."),
183 return "Mips Delay Slot Filler"
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
168 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
172 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
214 /// MipsOperand - Instances of this class represent a parsed Mips machine
452 NopInst.setOpcode(Mips::SLL);
453 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
454 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
505 case Mips::LoadImm32Reg:
506 case Mips::LoadAddr32Imm:
507 case Mips::LoadAddr32Reg
[all...] |
| /external/llvm/include/llvm/Config/ |
| llvm-platform-config.h | 69 #define LLVM_NATIVE_ARCH Mips
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
10 // This file is part of the Mips Disassembler.
14 #include "Mips.h"
31 /// MipsDisassemblerBase - a disasembler class for Mips.
346 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
357 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
376 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
388 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
399 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
410 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo)
[all...] |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/lib/gcc/i686-linux/4.4.3/include-fixed/X11/ |
| Xosdefs.h | 80 #ifdef Mips
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/X11/ |
| Xosdefs.h | 71 #ifdef Mips
|
| Xarch.h | 44 #if defined(NCR) || defined(Mips) || defined(__sgi)
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/lib/gcc/i686-linux/4.6.x-google/include-fixed/X11/ |
| Xosdefs.h | 80 #ifdef Mips
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/X11/ |
| Xosdefs.h | 71 #ifdef Mips
|
| Xarch.h | 44 #if defined(NCR) || defined(Mips) || defined(__sgi)
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/X11/ |
| Xosdefs.h | 71 #ifdef Mips
|
| Xarch.h | 44 #if defined(NCR) || defined(Mips) || defined(__sgi)
|
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.h | 1 //=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==//
10 // This class prints a Mips MCInst to a .s file.
22 namespace Mips {
23 // Mips Branch Codes
32 // Mips Condition Codes
73 const char *MipsFCCToString(Mips::CondCode CC);
74 } // end namespace Mips
|
| /external/llvm/ |
| shared_llvm.mk | 67 # Host build pulls in all ARM, Mips, X86 components.
92 # Device build selectively pulls in ARM, Mips, X86 components.
102 ifeq ($(TARGET_ARCH),mips)
|
| /external/clang/include/clang/Basic/ |
| TargetBuiltins.h | 125 /// \brief MIPS builtins
126 namespace Mips {
|
