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  /external/llvm/lib/CodeGen/
StrongPHIElimination.cpp 249 unsigned SrcReg = SrcMO.getReg();
250 addReg(SrcReg);
251 unionRegs(DestReg, SrcReg);
253 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
291 unsigned SrcReg = BBI->getOperand(i).getReg();
292 addReg(SrcReg);
293 unionRegs(DestReg, SrcReg);
308 unsigned SrcReg = PHI->getOperand(1).getReg();
309 unsigned SrcColor = getRegColor(SrcReg);
312 NewReg = SrcReg;
    [all...]
OptimizePHIs.cpp 99 unsigned SrcReg = MI->getOperand(i).getReg();
100 if (SrcReg == DstReg)
102 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
120 SingleValReg = SrcReg;
PeepholeOptimizer.cpp 150 unsigned SrcReg, DstReg, SubIdx;
151 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
155 TargetRegisterInfo::isPhysicalRegister(SrcReg))
158 if (MRI->hasOneNonDBGUse(SrcReg))
169 // The ext instr may be operating on a sub-register of SrcReg as well.
172 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
173 // SrcReg:SubIdx should be replaced.
175 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0;
193 UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end();
205 // Only accept uses of SrcReg:SubIdx
    [all...]
  /external/llvm/lib/Target/Mips/
MipsInstrInfo.h 87 unsigned SrcReg, bool isKill, int FrameIndex,
90 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
103 unsigned SrcReg, bool isKill, int FrameIndex,
MipsSEInstrInfo.h 49 unsigned DestReg, unsigned SrcReg,
54 unsigned SrcReg, bool isKill, int FrameIndex,
Mips16InstrInfo.h 48 unsigned DestReg, unsigned SrcReg,
53 unsigned SrcReg, bool isKill, int FrameIndex,
  /external/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 43 unsigned DestReg, unsigned SrcReg,
47 if (DestReg == AArch64::XSP || SrcReg == AArch64::XSP) {
50 .addReg(SrcReg)
53 } else if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
56 .addReg(SrcReg)
60 assert(AArch64::GPR64RegClass.contains(SrcReg));
64 .addReg(SrcReg);
65 } else if (SrcReg == AArch64::NZCV) {
71 assert(AArch64::GPR64RegClass.contains(SrcReg));
75 assert(AArch64::GPR32RegClass.contains(SrcReg));
    [all...]
  /external/llvm/lib/Target/XCore/
XCoreRegisterInfo.h 34 unsigned SrcReg, int Offset, DebugLoc dl) const;
XCoreInstrInfo.cpp 336 unsigned DestReg, unsigned SrcReg,
339 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
343 .addReg(SrcReg, getKillRegState(KillSrc))
348 if (GRDest && SrcReg == XCore::SP) {
355 .addReg(SrcReg, getKillRegState(KillSrc));
363 unsigned SrcReg, bool isKill,
371 .addReg(SrcReg, getKillRegState(isKill))
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
radeon_dataflow_deadcode.c 43 unsigned char SrcReg[3];
186 unsigned int newsrcmask = srcmasks[src] & ~insts->SrcReg[src];
187 insts->SrcReg[src] |= newsrcmask;
191 refmask |= 1 << GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan);
200 mark_used(s, inst->U.I.SrcReg[src].File, inst->U.I.SrcReg[src].Index, refmask);
202 if (inst->U.I.SrcReg[src].RelAddr)
260 ptr->U.I.SrcReg[src].File,
261 ptr->U.I.SrcReg[src].Index,
353 SET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan, RC_SWIZZLE_UNUSED)
    [all...]
radeon_program.c 177 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
178 inst->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_XYZW;
179 inst->U.I.SrcReg[2].Swizzle = RC_SWIZZLE_XYZW;
  /external/mesa3d/src/gallium/drivers/r300/compiler/
radeon_dataflow_deadcode.c 43 unsigned char SrcReg[3];
186 unsigned int newsrcmask = srcmasks[src] & ~insts->SrcReg[src];
187 insts->SrcReg[src] |= newsrcmask;
191 refmask |= 1 << GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan);
200 mark_used(s, inst->U.I.SrcReg[src].File, inst->U.I.SrcReg[src].Index, refmask);
202 if (inst->U.I.SrcReg[src].RelAddr)
260 ptr->U.I.SrcReg[src].File,
261 ptr->U.I.SrcReg[src].Index,
353 SET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan, RC_SWIZZLE_UNUSED)
    [all...]
radeon_program.c 177 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
178 inst->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_XYZW;
179 inst->U.I.SrcReg[2].Swizzle = RC_SWIZZLE_XYZW;
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
brw_wm_fp.c 226 inst->SrcReg[0] = src0;
227 inst->SrcReg[1] = src1;
228 inst->SrcReg[2] = src2;
559 struct prog_src_register src0 = inst->SrcReg[0];
560 struct prog_src_register src1 = inst->SrcReg[1];
590 swz->SrcReg[0].Negate &= ~NEGATE_X;
623 struct prog_src_register src0 = inst->SrcReg[0];
649 swz->SrcReg[0].Negate = NEGATE_NONE;
688 struct prog_src_register src0 = inst->SrcReg[0];
701 out->SrcReg[0].Negate = NEGATE_NONE
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_wm_fp.c 226 inst->SrcReg[0] = src0;
227 inst->SrcReg[1] = src1;
228 inst->SrcReg[2] = src2;
559 struct prog_src_register src0 = inst->SrcReg[0];
560 struct prog_src_register src1 = inst->SrcReg[1];
590 swz->SrcReg[0].Negate &= ~NEGATE_X;
623 struct prog_src_register src0 = inst->SrcReg[0];
649 swz->SrcReg[0].Negate = NEGATE_NONE;
688 struct prog_src_register src0 = inst->SrcReg[0];
701 out->SrcReg[0].Negate = NEGATE_NONE
    [all...]
  /external/llvm/lib/Target/MSP430/
MSP430InstrInfo.cpp 36 unsigned SrcReg, bool isKill, int FrameIdx,
53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
90 unsigned DestReg, unsigned SrcReg,
93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
101 .addReg(SrcReg, getKillRegState(KillSrc));
  /external/llvm/lib/Target/Hexagon/
HexagonExpandPredSpillCode.cpp 87 // STriw_pred [R30], ofst, SrcReg;
93 int SrcReg = MI->getOperand(2).getReg();
94 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
105 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
114 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
123 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 645 unsigned DestReg, unsigned SrcReg,
648 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
652 .addReg(SrcReg, getKillRegState(KillSrc))));
657 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
666 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
668 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
673 MIB.addReg(SrcReg, getKillRegState(KillSrc));
675 MIB.addReg(SrcReg, getKillRegState(KillSrc));
686 if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
688 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
AMDGPUInstrInfo.h 51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
75 unsigned DestReg, unsigned SrcReg,
80 unsigned SrcReg, bool isKill, int FrameIndex,
  /external/chromium_org/third_party/mesa/src/src/mesa/main/
nvprogram.c 541 inst->SrcReg[0].File = PROGRAM_TEMPORARY;
542 inst->SrcReg[0].Index = 0;
543 inst->SrcReg[0].Swizzle = MAKE_SWIZZLE4(SWIZZLE_ZERO,
554 inst->SrcReg[0].File = PROGRAM_TEMPORARY;
555 inst->SrcReg[0].Index = 0;
556 inst->SrcReg[0].Swizzle = SWIZZLE_XXXX;
575 if (inst->SrcReg[0].File == PROGRAM_TEMPORARY) {
577 inst->SrcReg[0].Index + 1);
579 if (inst->SrcReg[1].File == PROGRAM_TEMPORARY) {
581 inst->SrcReg[1].Index + 1)
    [all...]
  /external/llvm/lib/Target/R600/
AMDGPUInstrInfo.h 53 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
77 unsigned DestReg, unsigned SrcReg,
82 unsigned SrcReg, bool isKill, int FrameIndex,
  /external/mesa3d/src/gallium/drivers/radeon/
AMDGPUInstrInfo.h 51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
75 unsigned DestReg, unsigned SrcReg,
80 unsigned SrcReg, bool isKill, int FrameIndex,
  /external/mesa3d/src/mesa/main/
nvprogram.c 541 inst->SrcReg[0].File = PROGRAM_TEMPORARY;
542 inst->SrcReg[0].Index = 0;
543 inst->SrcReg[0].Swizzle = MAKE_SWIZZLE4(SWIZZLE_ZERO,
554 inst->SrcReg[0].File = PROGRAM_TEMPORARY;
555 inst->SrcReg[0].Index = 0;
556 inst->SrcReg[0].Swizzle = SWIZZLE_XXXX;
575 if (inst->SrcReg[0].File == PROGRAM_TEMPORARY) {
577 inst->SrcReg[0].Index + 1);
579 if (inst->SrcReg[1].File == PROGRAM_TEMPORARY) {
581 inst->SrcReg[1].Index + 1)
    [all...]
  /external/llvm/lib/Target/X86/
X86InstrInfo.h 171 unsigned &SrcReg, unsigned &DstReg,
248 unsigned DestReg, unsigned SrcReg,
252 unsigned SrcReg, bool isKill, int FrameIndex,
256 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
389 /// in SrcReg and SrcReg2 if having two register operands, and the value it
392 virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
399 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
  /external/llvm/lib/Target/SystemZ/
SystemZElimCompare.cpp 192 unsigned SrcReg = Compare->getOperand(0).getReg();
195 if (getRegReferences(MBBI, SrcReg))
329 unsigned SrcReg = Compare->getOperand(0).getReg();
338 if (resultTests(MI, SrcReg, SrcSubReg)) {
353 SrcRefs |= getRegReferences(MI, SrcReg);
382 unsigned SrcReg = Compare->getOperand(0).getReg();
387 if (MBBI->modifiesRegister(SrcReg, TRI) ||
414 // Clear any intervening kills of SrcReg and SrcReg2.
417 MBBI->clearRegisterKills(SrcReg, TRI);

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