| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 99 .addReg(MSP430::SPW).addImm(NumBytes);
162 .addReg(MSP430::SPW).addImm(CSSize);
171 .addReg(MSP430::SPW).addImm(NumBytes);
249 .addReg(MSP430::SPW).addImm(Amount);
258 .addReg(MSP430::SPW).addImm(Amount);
276 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
|
| MSP430InstrInfo.cpp | 52 .addFrameIndex(FrameIdx).addImm(0)
56 .addFrameIndex(FrameIdx).addImm(0)
80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
278 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 75 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
102 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
|
| ARMExpandPseudoInsts.cpp | 558 MIB.addImm(Lane);
635 LO16 = LO16.addImm(SOImmValV1);
636 HI16 = HI16.addImm(SOImmValV2)
[all...] |
| ARMBaseInstrInfo.cpp | 174 .addReg(BaseReg).addImm(Amt)
175 .addImm(Pred).addReg(0).addReg(0);
181 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
182 .addImm(Pred).addReg(0).addReg(0);
187 .addImm(Pred).addReg(0).addReg(0);
197 .addReg(BaseReg).addImm(Amt)
198 .addImm(Pred).addReg(0).addReg(0);
203 .addImm(Pred).addReg(0).addReg(0);
213 .addReg(WBReg).addImm(0).addImm(Pred)
[all...] |
| ARMFastISel.cpp | 379 .addImm(Imm));
383 .addImm(Imm));
425 .addImm(Imm));
430 .addImm(Imm));
446 .addImm(Imm));
449 .addImm(Imm));
465 .addImm(Imm1).addImm(Imm2));
468 .addImm(Imm1).addImm(Imm2))
[all...] |
| ARMFrameLowering.cpp | 226 .addFrameIndex(FramePtrSpillFI).addImm(0)
301 .addImm(MaxAlign-1)));
314 .addImm(MaxAlign-1)));
332 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
418 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
460 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
640 .addImm(-4);
718 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
720 MIB.addImm(4);
779 .addImm(8 * NumAlignedDPRCS2Regs)))
[all...] |
| Thumb1RegisterInfo.cpp | 80 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
118 .addImm(NumBytes).setMIFlags(MIFlags);
121 .addImm(NumBytes).setMIFlags(MIFlags);
245 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
264 MIB.addReg(DestReg).addImm(ThisVal);
272 MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
294 .addImm(((unsigned)NumBytes) & 3)
315 .addImm(ThisVal));
391 .addImm(Offset / Scale));
418 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask))
[all...] |
| ARMLoadStoreOptimizer.cpp | 339 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset)
340 .addImm(Pred).addReg(PredReg).addReg(0);
351 .addImm(Pred).addReg(PredReg);
780 .addImm(Pred).addReg(PredReg);
933 .addImm(Pred).addReg(PredReg)
943 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
948 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 56 .addImm(Offset);
72 .addImm(Offset);
130 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
163 .addImm(0);
226 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
232 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
338 .addImm(Amount);
343 .addImm(Amount);
|
| XCoreInstrInfo.cpp | 344 .addImm(0);
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
373 .addImm(0);
386 .addImm(0);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 285 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
344 .addImm(CCValid).addImm(CCMask)
528 .addImm(Start).addImm(End + 128).addImm(0);
563 .addImm(0).addReg(0);
571 .addFrameIndex(FrameIndex).addImm(0).addReg(0);
590 .addFrameIndex(FrameIndex).addImm(0).addImm(Size
[all...] |
| SystemZISelLowering.cpp | [all...] |
| SystemZLongBranch.cpp | 348 .addImm(-1);
350 .addImm(SystemZ::CCMASK_ICMP)
351 .addImm(SystemZ::CCMASK_CMP_NE)
368 .addImm(SystemZ::CCMASK_ICMP)
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 57 MachineInstrBuilder(MI).addImm(Imm);
|
| R600ISelLowering.cpp | 68 .addImm(0) // Flags
79 .addImm(0) // Flags
91 .addImm(0) // Flags
133 .addImm(2);
141 .addImm(EOP); // Set End of program bit
210 .addImm(OPCODE_IS_ZERO)
211 .addImm(0); // Flags
224 .addImm(OPCODE_IS_ZERO_INT)
225 .addImm(0); // Flags
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitTFRCondSets.cpp | 141 addImm(MI->getOperand(3).getImm());
162 addImm(MI->getOperand(2).getImm());
191 DestReg).addReg(SrcReg1).addImm(Immed1);
194 DestReg).addReg(SrcReg1).addImm(Immed2);
|
| HexagonCopyToCombine.cpp | 570 .addImm(LoOperand.getImm());
575 .addImm(HiOperand.getImm())
585 .addImm(HiOperand.getImm())
586 .addImm(LoOperand.getImm());
593 .addImm(HiOperand.getImm())
594 .addImm(LoOperand.getImm());
601 .addImm(HiOperand.getImm())
602 .addImm(LoOperand.getImm());
626 .addImm(HiOperand.getImm())
653 .addImm(LoOperand.getImm())
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 288 .addImm(FrameSize);
291 .addImm(0)
295 .addImm(0)
312 .addImm(~(MaxAlign-1));
328 .addImm(maxCallFrameSize);
337 .addImm(~(MaxAlign-1));
353 .addImm(maxCallFrameSize);
399 .addImm(getEncodingValue(SrcReg) * 4)
400 .addImm(0)
401 .addImm(31)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 57 MachineInstrBuilder(MI).addImm(Imm);
|
| R600ISelLowering.cpp | 68 .addImm(0) // Flags
79 .addImm(0) // Flags
91 .addImm(0) // Flags
133 .addImm(2);
141 .addImm(EOP); // Set End of program bit
210 .addImm(OPCODE_IS_ZERO)
211 .addImm(0); // Flags
224 .addImm(OPCODE_IS_ZERO_INT)
225 .addImm(0); // Flags
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 578 .addImm(ExtraInfo);
658 TII.get(TargetOpcode::DBG_VALUE)).addOperand(*Op).addImm(0)
675 .addReg(0U).addImm(DI->getOffset())
680 .addCImm(CI).addImm(DI->getOffset())
684 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
688 .addFPImm(CF).addImm(DI->getOffset())
[all...] |
| /external/llvm/lib/Target/R600/ |
| SILowerControlFlow.cpp | 156 .addImm(3)
161 .addImm(0)
162 .addImm(0x09) // V_008DFC_SQ_EXP_NULL
163 .addImm(0)
164 .addImm(1)
165 .addImm(1)
305 .addImm(0)
362 .addImm(-7)
508 AMDGPU::M0).addImm(0xffffffff);
|
| R600InstrInfo.cpp | 86 MIB.addImm(Imm);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 191 .addImm(ThisVal);
715 .addImm(-TailCallReturnAddrDelta)
840 .addImm(-MaxAlign)
[all...] |
