| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 122 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
126 HEXAGON_RESERVED_REG_1).addImm(NumBytes);
132 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
|
| HexagonFixupHwLoops.cpp | 174 .addImm(MII->getOperand(1).getImm());
|
| HexagonHardwareLoops.cpp | 792 SubIB.addImm(EndV)
796 .addImm(-StartV);
814 .addImm(AdjV);
835 .addImm(Shift);
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 154 .addImm(0); // Flag
|
| R600InstrInfo.cpp | 61 .addImm(0) // Flag
73 .addImm(0) // Flag
84 MachineInstrBuilder(MI).addImm(Imm);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430BranchSelector.cpp | 156 .addImm(4).addOperand(Cond[0]);
|
| MSP430RegisterInfo.cpp | 146 .addReg(DstReg).addImm(-Offset);
149 .addReg(DstReg).addImm(Offset);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 154 .addImm(0); // Flag
|
| R600InstrInfo.cpp | 61 .addImm(0) // Flag
73 .addImm(0) // Flag
84 MachineInstrBuilder(MI).addImm(Imm);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 292 .addImm(0);
294 .addImm(RSRC_DATA_FORMAT >> 32);
297 .addImm(AMDGPU::sub0)
299 .addImm(AMDGPU::sub1);
302 .addImm(AMDGPU::sub0_sub1)
304 .addImm(AMDGPU::sub2_sub3);
315 .addImm(0) /* src2 */
316 .addImm(0) /* ABS */
317 .addImm(0) /* CLAMP */
318 .addImm(0) /* OMOD *
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 182 .addImm(CC);
232 MIB.addImm(Mask);
|
| A15SDOptimizer.cpp | 443 .addImm(Lane));
477 .addImm(ARM::dsub_0)
479 .addImm(ARM::dsub_1);
497 .addImm(1));
513 .addImm(Lane);
|
| MLxExpansionPass.cpp | 296 MIB.addImm(LaneImm);
297 MIB.addImm(Pred).addReg(PredReg);
309 MIB.addImm(Pred).addReg(PredReg);
|
| ARMInstrInfo.cpp | 130 MIB.addImm(0);
|
| ARMISelLowering.cpp | [all...] |
| ARMConstantIslandPass.cpp | 546 .addImm(i).addConstantPoolIndex(i).addImm(Size);
[all...] |
| ARMBaseRegisterInfo.cpp | 401 .addImm(0).addImm(Pred).addReg(PredReg)
581 .addFrameIndex(FrameIdx).addImm(Offset));
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 113 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
133 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
209 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
241 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
323 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
358 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
361 .addImm(SignExtend64<16>(Inst->ImmOpnd));
366 .addImm(SignExtend64<16>(Inst->ImmOpnd));
|
| MipsISelLowering.cpp | 783 .addOperand(MI->getOperand(2)).addReg(Mips::ZERO).addImm(7);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FixupLEAs.cpp | 107 .addOperand(Src).addImm(1).addReg(0).addImm(0).addReg(0);
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 81 /// addImm - Add a new immediate operand.
83 const MachineInstrBuilder &addImm(int64_t Val) const {
198 return addImm(Disp.getImm() + off);
353 .addImm(Offset)
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 112 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 117 .addReg(BasePtr).addImm(HighOffset).addReg(0);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 367 MIB.addImm(C->getSExtValue());
547 MIB.addImm(SD->getZExtValue());
554 MIB.addImm(SubIdx);
643 .addFrameIndex(SD->getFrameIx()).addImm(Offset).addMetadata(MDPtr);
668 MIB.addImm(CI->getSExtValue());
682 MIB.addImm(Offset);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
