| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 68 static CCValAssign getReg(unsigned ValNo, MVT ValVT,
86 Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
|
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 281 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
542 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
|
| MCInst.h | 62 /// getReg - Returns the register number.
63 unsigned getReg() const {
|
| /external/llvm/lib/CodeGen/ |
| PrologEpilogInserter.cpp | 249 unsigned Reg = I->getReg();
314 EntryBlock->addLiveIn(CSI[i].getReg());
317 unsigned Reg = CSI[i].getReg();
344 unsigned Reg = CSI[i].getReg();
389 MBB->addLiveIn(blockCSI[i].getReg());
392 unsigned Reg = blockCSI[i].getReg();
443 unsigned Reg = blockCSI[i].getReg();
[all...] |
| UnreachableBlockElim.cpp | 191 unsigned Input = phi->getOperand(1).getReg();
192 unsigned Output = phi->getOperand(0).getReg();
|
| ExecutionDepsFix.cpp | 466 int rx = regIndex(MO.getReg());
515 int rx = regIndex(mo.getReg());
524 int rx = regIndex(mo.getReg());
544 int rx = regIndex(mo.getReg());
636 int rx = regIndex(mo.getReg());
|
| PostRASchedulerList.cpp | 444 if (LiveRegs.test(MO.getReg())) {
453 const unsigned SuperReg = MO.getReg();
493 unsigned Reg = MO.getReg();
512 unsigned Reg = MO.getReg();
547 unsigned Reg = MO.getReg();
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| TailDuplication.cpp | 282 unsigned Dst = Copy->getOperand(0).getReg();
283 unsigned Src = Copy->getOperand(1).getReg();
361 unsigned SrcReg = MI.getOperand(i).getReg();
390 unsigned DefReg = MI->getOperand(0).getReg();
393 unsigned SrcReg = MI->getOperand(SrcOpIdx).getReg();
427 unsigned Reg = MO.getReg();
474 unsigned Reg = MO0.getReg();
[all...] |
| Spiller.cpp | 111 if (!op.isReg() || op.getReg() != li->reg)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 82 O << HexagonInstPrinter::getRegisterName(MO.getReg());
258 O << HexagonInstPrinter::getRegisterName(MO1.getReg())
|
| HexagonCallingConvLower.cpp | 102 addLoc(CCValAssign::getReg(0, MVT::i32, Reg, MVT::i32,
108 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
|
| HexagonInstrInfo.cpp | 84 return MI->getOperand(0).getReg();
108 return MI->getOperand(2).getReg();
158 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
163 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
353 SrcReg = MI->getOperand(1).getReg();
362 SrcReg = MI->getOperand(1).getReg();
371 SrcReg = MI->getOperand(1).getReg();
392 SrcReg2 = MI->getOperand(2).getReg();
872 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
915 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef()
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 32 return MI.getOperand(OpNo).getReg() == R;
165 printRegName(O, Op.getReg());
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 125 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
145 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
169 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
198 unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
211 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
318 unsigned Reg = I->getReg();
450 unsigned Reg = CSI[i].getReg();
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 300 unsigned NegSizeReg = MI.getOperand(1).getReg();
326 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
351 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
383 unsigned SrcReg = MI.getOperand(0).getReg();
427 unsigned DestReg = MI.getOperand(0).getReg();
466 unsigned SrcReg = MI.getOperand(0).getReg();
491 unsigned DestReg = MI.getOperand(0).getReg();
678 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUAsmPrinter.cpp | 98 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
166 reg = MO.getReg();
|
| /external/llvm/lib/Target/R600/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 31 switch (Op.getReg()) {
34 default: O << getRegisterName(Op.getReg()); break;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 289 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
534 SUnit *RegDef = LiveRegDefs[I->getReg()]; (void)RegDef;
537 LiveRegDefs[I->getReg()] = I->getSUnit();
538 if (!LiveRegGens[I->getReg()]) {
540 LiveRegGens[I->getReg()] = SU;
741 // LiveRegDegs[I->getReg()] != SU when SU is a two-address node.
742 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) {
745 LiveRegDefs[I->getReg()] = NULL;
746 LiveRegGens[I->getReg()] = NULL;
747 releaseInterferences(I->getReg());
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 349 unsigned Reg = MI->getOperand(idx).getReg();
425 switch (MO2.getReg()) {
462 PMO.setReg(Pred[2].getReg());
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 328 unsigned Reg0 = MI->getOperand(0).getReg();
329 unsigned Reg1 = MI->getOperand(1).getReg();
375 unsigned Reg = Op.getReg();
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 349 unsigned Reg = MI->getOperand(idx).getReg();
425 switch (MO2.getReg()) {
462 PMO.setReg(Pred[2].getReg());
|
| /dalvik/dx/src/com/android/dx/cf/code/ |
| OneLocalsArray.java | 136 set(spec.getReg(), spec);
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| PhiTypeResolver.java | 101 worklist.set(resultReg.getReg());
|
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| PhiTypeResolver.java | 102 worklist.set(resultReg.getReg());
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64MCInstLower.cpp | 107 MCOp = MCOperand::CreateReg(MO.getReg());
|
