| /external/llvm/test/MC/Mips/ |
| micromips-shift-instructions.s | 8 # CHECK: sllv $2, $3, $5 # encoding: [0x10,0x10,0x65,0x00]
16 sllv $2, $3, $5
|
| mips-alu-instructions.s | 22 # CHECK: sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
53 sllv $2, $3, $5
|
| mips64-alu-instructions.s | 20 # CHECK: sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
48 sllv $2, $3, $5
|
| /external/llvm/test/CodeGen/Mips/ |
| atomic.ll | 118 ; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
120 ; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]
144 ; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
146 ; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]]
175 ; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
177 ; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]
201 ; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]]
203 ; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]]
232 ; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
234 ; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]
[all...] |
| sll2.ll | 12 ; 16: sllv ${{[0-9]+}}, ${{[0-9]+}}
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-mips.cc | 224 COMPARE(sllv(a0, a1, a2),
225 "00c52004 sllv a0, a1, a2");
226 COMPARE(sllv(s0, s1, s2),
227 "02518004 sllv s0, s1, s2");
228 COMPARE(sllv(t2, t3, t4),
229 "018b5004 sllv t2, t3, t4");
230 COMPARE(sllv(v0, v1, fp),
231 "03c31004 sllv v0, v1, fp");
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 234 COMPARE(sllv(a0, a1, a2),
235 "00c52004 sllv a0, a1, a2");
236 COMPARE(sllv(s0, s1, s2),
237 "02518004 sllv s0, s1, s2");
238 COMPARE(sllv(t2, t3, t4),
239 "018b5004 sllv t2, t3, t4");
240 COMPARE(sllv(v0, v1, fp),
241 "03c31004 sllv v0, v1, fp");
|
| /external/valgrind/main/none/tests/mips32/ |
| MIPS32int.c | [all...] |
| MIPS32int.stdout.exp | [all...] |
| MIPS32int.stdout.exp-BE | [all...] |
| MIPS32int.stdout.exp-mips32 | [all...] |
| /external/kernel-headers/original/asm-mips/ |
| asm.h | 263 #define INT_SLLV sllv
300 #define LONG_SLLV sllv
349 #define PTR_SLLV sllv
|
| /external/llvm/lib/Target/Mips/ |
| MicroMipsInstrInfo.td | 47 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd>,
|
| /bionic/libc/kernel/arch-mips/asm/ |
| asm.h | 117 #define INT_SLLV sllv
157 #define LONG_SLLV sllv
210 #define PTR_SLLV sllv
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| asm.h | 117 #define INT_SLLV sllv
157 #define LONG_SLLV sllv
210 #define PTR_SLLV sllv
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| asm.h | 117 #define INT_SLLV sllv
157 #define LONG_SLLV sllv
210 #define PTR_SLLV sllv
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
| asm.h | 117 #define INT_SLLV sllv
157 #define LONG_SLLV sllv
210 #define PTR_SLLV sllv
|
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/ |
| asm.h | 117 #define INT_SLLV sllv
157 #define LONG_SLLV sllv
210 #define PTR_SLLV sllv
|
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/ |
| asm.h | 117 #define INT_SLLV sllv
157 #define LONG_SLLV sllv
210 #define PTR_SLLV sllv
|
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/ |
| asm.h | 117 #define INT_SLLV sllv
157 #define LONG_SLLV sllv
210 #define PTR_SLLV sllv
|
| /system/core/include/private/pixelflinger/ |
| ggl_fixed.h | 332 "sllv %[tmp2],%[tmp2],%[tmp1] \t\n"
350 "sllv %[tmp2],%[tmp2],%[tmp1] \t\n"
404 "sllv %[tmp2],%[tmp2],%[tmp1] \t\n"
422 "sllv %[tmp2],%[tmp2],%[tmp1] \t\n"
|
| /external/chromium_org/v8/src/mips/ |
| constants-mips.cc | 250 case SLLV:
|
| /external/v8/src/mips/ |
| constants-mips.cc | 246 case SLLV:
|
| /art/runtime/ |
| disassembler_mips.cc | 58 { kRTypeMask, 4, "sllv", "DTS", },
|
| /art/compiler/utils/mips/ |
| assembler_mips.h | 246 void Sllv(Register rd, Register rs, Register rt);
|
