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      1 let isCodeGenOnly = 1 in {
      2   /// Arithmetic Instructions (ALU Immediate)
      3   def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
      4                  ADDI_FM_MM<0xc>;
      5   def ADDi_MM  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
      6                  ADDI_FM_MM<0x4>;
      7   def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
      8                  SLTI_FM_MM<0x24>;
      9   def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
     10                  SLTI_FM_MM<0x2c>;
     11   def ANDi_MM  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
     12                  ADDI_FM_MM<0x34>;
     13   def ORi_MM   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
     14                  ADDI_FM_MM<0x14>;
     15   def XORi_MM  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
     16                  ADDI_FM_MM<0x1c>;
     17   def LUi_MM   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
     18 
     19   /// Arithmetic Instructions (3-Operand, R-Type)
     20   def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
     21   def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
     22   def MUL_MM   : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
     23   def ADD_MM   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
     24   def SUB_MM   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
     25   def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
     26   def SLTu_MM  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
     27                  ADD_FM_MM<0, 0x390>;
     28   def AND_MM   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IIAlu, and>,
     29                  ADD_FM_MM<0, 0x250>;
     30   def OR_MM    : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IIAlu, or>,
     31                  ADD_FM_MM<0, 0x290>;
     32   def XOR_MM   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IIAlu, xor>,
     33                  ADD_FM_MM<0, 0x310>;
     34   def NOR_MM   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
     35   def MULT_MM  : MMRel, Mult<"mult", IIImul, GPR32Opnd, [HI, LO]>,
     36                  MULT_FM_MM<0x22c>;
     37   def MULTu_MM : MMRel, Mult<"multu", IIImul, GPR32Opnd, [HI, LO]>,
     38                  MULT_FM_MM<0x26c>;
     39 
     40   /// Shift Instructions
     41   def SLL_MM   : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd>,
     42                  SRA_FM_MM<0, 0>;
     43   def SRL_MM   : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd>,
     44                  SRA_FM_MM<0x40, 0>;
     45   def SRA_MM   : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd>,
     46                  SRA_FM_MM<0x80, 0>;
     47   def SLLV_MM  : MMRel, shift_rotate_reg<"sllv", GPR32Opnd>,
     48                  SRLV_FM_MM<0x10, 0>;
     49   def SRLV_MM  : MMRel, shift_rotate_reg<"srlv", GPR32Opnd>,
     50                  SRLV_FM_MM<0x50, 0>;
     51   def SRAV_MM  : MMRel, shift_rotate_reg<"srav", GPR32Opnd>,
     52                  SRLV_FM_MM<0x90, 0>;
     53   def ROTR_MM  : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd>,
     54                  SRA_FM_MM<0xc0, 0>;
     55   def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd>,
     56                  SRLV_FM_MM<0xd0, 0>;
     57 
     58   /// Load and Store Instructions - aligned
     59   defm LB_MM  : LoadM<"lb", GPR32Opnd, sextloadi8>, MMRel, LW_FM_MM<0x7>;
     60   defm LBu_MM : LoadM<"lbu", GPR32Opnd, zextloadi8>, MMRel, LW_FM_MM<0x5>;
     61   defm LH_MM  : LoadM<"lh", GPR32Opnd, sextloadi16>, MMRel, LW_FM_MM<0xf>;
     62   defm LHu_MM : LoadM<"lhu", GPR32Opnd, zextloadi16>, MMRel, LW_FM_MM<0xd>;
     63   defm LW_MM  : LoadM<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
     64   defm SB_MM  : StoreM<"sb", GPR32Opnd, truncstorei8>, MMRel, LW_FM_MM<0x6>;
     65   defm SH_MM  : StoreM<"sh", GPR32Opnd, truncstorei16>, MMRel, LW_FM_MM<0xe>;
     66   defm SW_MM  : StoreM<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
     67 }
     68