| /external/llvm/test/Transforms/InstCombine/ |
| vector-type.ll | 6 define i32 @vselect1(i32 %a.coerce, i32 %b.coerce, i32 %c.coerce) {
8 %0 = bitcast i32 %a.coerce to <2 x i16>
9 %1 = bitcast i32 %b.coerce to <2 x i16>
10 %2 = bitcast i32 %c.coerce to <2 x i16>
|
| /external/llvm/test/CodeGen/Mips/ |
| dsp-patterns-cmp-vselect.ll | 7 define { i32 } @select_v2q15_eq_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) {
9 %0 = bitcast i32 %a0.coerce to <2 x i16>
10 %1 = bitcast i32 %a1.coerce to <2 x i16>
11 %2 = bitcast i32 %a2.coerce to <2 x i16>
12 %3 = bitcast i32 %a3.coerce to <2 x i16>
24 define { i32 } @select_v2q15_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce)
[all...] |
| dsp-r2.ll | 3 define i64 @test__builtin_mips_dpa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
7 %1 = bitcast i32 %a1.coerce to <2 x i16>
8 %2 = bitcast i32 %a2.coerce to <2 x i16>
15 define i64 @test__builtin_mips_dps_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
19 %1 = bitcast i32 %a1.coerce to <2 x i16>
20 %2 = bitcast i32 %a2.coerce to <2 x i16>
27 define i64 @test__builtin_mips_mulsa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone
[all...] |
| dsp-r1.ll | 111 define i64 @test__builtin_mips_dpau_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
115 %1 = bitcast i32 %a1.coerce to <4 x i8>
116 %2 = bitcast i32 %a2.coerce to <4 x i8>
123 define i64 @test__builtin_mips_dpau_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
127 %1 = bitcast i32 %a1.coerce to <4 x i8>
128 %2 = bitcast i32 %a2.coerce to <4 x i8>
135 define i64 @test__builtin_mips_dpsu_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone
[all...] |
| dsp-patterns.ll | 37 define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
39 %0 = bitcast i32 %a.coerce to <2 x i16>
40 %1 = bitcast i32 %b.coerce to <2 x i16>
50 define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
52 %0 = bitcast i32 %a.coerce to <2 x i16>
53 %1 = bitcast i32 %b.coerce to <2 x i16>
68 define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) {
[all...] |
| spill-copy-acreg.ll | 27 define { i32 } @test_ccond_spill(i32 %a.coerce, i32 %b.coerce) {
29 %0 = bitcast i32 %a.coerce to <2 x i16>
30 %1 = bitcast i32 %b.coerce to <2 x i16>
|
| /external/clang/test/CodeGen/ |
| ppc64-struct-onevect.c | 12 // CHECK: define <4 x float> @foo(<4 x float> inreg %a.coerce)
13 // CHECK: ret <4 x float> %a.coerce
|
| incomplete-function-type-2.c | 5 // CHECK: define void @test10_foo({}* %p1.coerce) [[NUW:#[0-9]+]] {
|
| x86_32-arguments-nommx.c | 6 // CHECK: define i32 @a(i64 %x.coerce)
|
| x86_64-arguments-nacl.c | 38 // CHECK: define void @f8_2(i64 %a0.coerce)
49 // CHECK: define void @f10(i64 %a0.coerce)
57 // CHECK: define void @f12_1(i32 %a0.coerce)
|
| ppc64-struct-onefloat.c | 17 // CHECK: store float %a.coerce, float* %{{[a-zA-Z0-9.]+}}, align 1
19 // CHECK: store double %b.coerce, double* %{{[a-zA-Z0-9.]+}}, align 1
22 // CHECK: store float %d.coerce, float* %{{[a-zA-Z0-9.]+}}, align 1
25 // CHECK: store double %e.coerce, double* %{{[a-zA-Z0-9.]+}}, align 1
|
| x86_64-arguments.c | 58 // CHECK: define void @f10(i64 %a0.coerce)
66 // CHECK: define void @f12_1(i32 %a0.coerce)
97 // CHECK: define void @f18(i32 %a, i32 %f18_arg1.coerce)
183 // CHECK: define <4 x float> @f27(<4 x float> %X.coerce)
223 // CHECK: define <2 x float> @f32(<2 x float> %A.coerce, <2 x float> %B.coerce)
238 // CHECK: define i64 @f34(i64 %arg.coerce)
243 // CHECK: define i64 @f35(i64 %arg.coerce)
263 // CHECK: define double @f36(double %arg.coerce)
|
| arm-arguments.c | 161 // AAPCS: @f31([1 x i32] %s.coerce)
164 // AAPCS: store [1 x i32] %s.coerce, [1 x i32]*
165 // APCS-GNU: @f31([1 x i32] %s.coerce)
168 // APCS-GNU: store [1 x i32] %s.coerce, [1 x i32]*
173 // AAPCS: @f32([1 x i64] %s.coerce)
174 // APCS-GNU: @f32([2 x i32] %s.coerce)
|
| /external/llvm/test/CodeGen/PowerPC/ |
| varargs-struct-float.ll | 8 define void @foo(float inreg %s.coerce) nounwind {
11 %coerce.dive = getelementptr %struct.Sf1* %s, i32 0, i32 0
12 store float %s.coerce, float* %coerce.dive, align 1
13 %coerce.dive1 = getelementptr %struct.Sf1* %s, i32 0, i32 0
14 %0 = load float* %coerce.dive1, align 1
|
| /external/clang/test/CodeGenObjC/ |
| x86_64-struct-return-gc.m | 2 struct Coerce {
6 struct Coerce coerce_func(void);
10 struct Coerce c;
|
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/test/ |
| test_compare.py | 8 class Coerce:
13 return '<Coerce %s>' % self.arg
16 if isinstance(other, Coerce):
32 set1 = [2, 2.0, 2L, 2+0j, Coerce(2), Cmp(2.0)]
|
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/test/ |
| test_compare.py | 8 class Coerce:
13 return '<Coerce %s>' % self.arg
16 if isinstance(other, Coerce):
32 set1 = [2, 2.0, 2L, 2+0j, Coerce(2), Cmp(2.0)]
|
| /frameworks/rs/driver/runtime/ |
| allocation.ll | 4 declare i8* @rsOffset([1 x i32] %a.coerce, i32 %sizeOf, i32 %x, i32 %y, i32 %z)
30 define void @rsSetElementAtImpl_char([1 x i32] %a.coerce, i8 signext %val, i32 %x, i32 %y, i32 %z) #2 {
31 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #10
36 define signext i8 @rsGetElementAtImpl_char([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #3 {
37 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #10
43 define void @rsSetElementAtImpl_char2([1 x i32] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #2 {
44 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #10
50 define <2 x i8> @rsGetElementAtImpl_char2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #3 {
51 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #10
58 define void @rsSetElementAtImpl_char3([1 x i32] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #2
[all...] |
| /external/llvm/test/Transforms/LoopUnswitch/ |
| 2010-11-18-LCSSA.ll | 5 define void @func_67(i32 %p_68.coerce) nounwind {
14 %tobool.i = icmp eq i32 %p_68.coerce, 1
15 %xor4.i = xor i32 %p_68.coerce, 1
|
| /external/llvm/test/CodeGen/ARM/ |
| dagcombine-concatvector.ll | 10 define void @test1(i8* %arg, [4 x i64] %vec.coerce) {
12 %tmp = extractvalue [4 x i64] %vec.coerce, 0
15 %tmp4 = extractvalue [4 x i64] %vec.coerce, 1
|
| /external/clang/test/CodeGenCXX/ |
| blocks-cxx11.cpp | 53 // CHECK-NEXT: [[COERCE:%.*]] = bitcast
54 // CHECK-NEXT: [[CVAL:%.*]] = load i64* [[COERCE]]
79 // CHECK-NEXT: [[COERCE:%.*]] = bitcast { i32, i32 }* [[CSLOT]] to i64*
80 // CHECK-NEXT: [[CVAL:%.*]] = load i64* [[COERCE]],
|
| /external/llvm/test/CodeGen/X86/ |
| 3dnow-intrinsics.ll | 3 define <8 x i8> @test_pavgusb(x86_mmx %a.coerce, x86_mmx %b.coerce) nounwind readnone {
6 %0 = bitcast x86_mmx %a.coerce to <8 x i8>
7 %1 = bitcast x86_mmx %b.coerce to <8 x i8>
206 define <2 x float> @test_pi2fd(x86_mmx %a.coerce) nounwind readnone {
209 %0 = bitcast x86_mmx %a.coerce to <2 x i32>
218 define <4 x i16> @test_pmulhrw(x86_mmx %a.coerce, x86_mmx %b.coerce) nounwind readnone {
221 %0 = bitcast x86_mmx %a.coerce to <4 x i16>
222 %1 = bitcast x86_mmx %b.coerce to <4 x i16
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| bitfield-insert.ll | 8 define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone {
14 %f.coerce.fca.0.extract = extractvalue [1 x i64] %f.coerce, 0
15 %tmp.sroa.0.0.extract.trunc = trunc i64 %f.coerce.fca.0.extract to i32
21 %tmp1.sroa.1.1.insert.insert = and i64 %f.coerce.fca.0.extract, 4294967040
|
| /external/chromium_org/third_party/JSON/JSON-2.59/t/ |
| 02_error.t | 44 eval { JSON->new->decode (\5) }; ok !!$@; # Can't coerce readonly
47 eval { JSON->new->decode (*STDERR) }; ok !!$@; # cannot coerce GLOB
|
| x02_error.t | 48 eval { JSON->new->decode (\5) }; ok !!$@; # Can't coerce readonly
51 eval { JSON->new->decode (*STDERR) }; ok !!$@; # cannot coerce GLOB
|
