| /dalvik/vm/mterp/common/ |
| mips-defines.h | 1 #define fcc0 $fcc0 macro
|
| /external/valgrind/main/none/tests/mips32/ |
| MoveIns.c | 370 TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0, 0xffffffff, t0, t1, 1);
371 TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0xffffffff, 0xffffffff, t0, t1, 0);
372 TESTINSNMOVE2("movf $t0, $t1, $fcc0", 555, 0xffffffff, t0, t1, 1);
373 TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0, 5, t0, t1, 0);
374 TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0, -1, t0, t1, 1);
375 TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0xffffffff, 25, t0, t1, 0);
376 TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0xffffffff, 0, t0, t1, 1);
377 TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0xffffffff, 66, t0, t1, 0);
388 TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 0);
389 TESTINSNMOVE2s("movf.s $f4, $f6, $fcc0", f4, f6, 1, 4)
[all...] |
| MoveIns.stdout.exp | 114 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
115 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
116 movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
117 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
118 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
119 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
120 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
121 movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
131 movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
132 movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc:
[all...] |
| MoveIns.stdout.exp-BE | 114 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
115 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
116 movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
117 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
118 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
119 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
120 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
121 movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
131 movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
132 movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc:
[all...] |
| /dalvik/vm/compiler/template/mips/ |
| TEMPLATE_CMPL_FLOAT_VFP.S | 53 c.olt.s fcc0, fs0, fs1 #Is fs0 < fs1
55 bc1t fcc0, ${opcode}_finish
56 c.olt.s fcc0, fs1, fs0
58 bc1t fcc0, ${opcode}_finish
59 c.eq.s fcc0, fs0, fs1
61 bc1t fcc0, ${opcode}_finish
|
| TEMPLATE_CMPL_DOUBLE_VFP.S | 53 c.olt.d fcc0, fs0, fs1 # Is fs0 < fs1
55 bc1t fcc0, ${opcode}_finish
56 c.olt.d fcc0, fs1, fs0
58 bc1t fcc0, ${opcode}_finish
59 c.eq.d fcc0, fs0, fs1
61 bc1t fcc0, ${opcode}_finish
|
| TEMPLATE_FLOAT_TO_INT_VFP.S | 36 c.ole.s fcc0, fa1, fa0
41 c.ole.s fcc0, fa0, fa1
46 c.un.s fcc0, fa0, fa1
|
| fbinop.S | 31 c.eq.s fcc0, ft0, fa1 # condition bit and comparision with 0
32 bc1t fcc0, common_errDivideByZero
|
| TEMPLATE_DOUBLE_TO_INT_VFP.S | 52 c.ole.d fcc0, fa1, fa0
58 c.ole.d fcc0, fa0, fa1
63 c.un.d fcc0, fa0, fa1
|
| fbinopWide.S | 38 c.eq.d fcc0, fa1, ft0
39 bc1t fcc0, common_errDivideByZero
|
| /dalvik/vm/mterp/mips/ |
| OP_CMPL_DOUBLE.S | 41 c.olt.d fcc0, ft0, ft1
43 bc1t fcc0, ${opcode}_finish
44 c.olt.d fcc0, ft1, ft0
46 bc1t fcc0, ${opcode}_finish
47 c.eq.d fcc0, ft0, ft1
49 bc1t fcc0, ${opcode}_finish
|
| OP_CMPL_FLOAT.S | 50 c.olt.s fcc0, ft0, ft1 # Is ft0 < ft1
52 bc1t fcc0, ${opcode}_finish
53 c.olt.s fcc0, ft1, ft0
55 bc1t fcc0, ${opcode}_finish
56 c.eq.s fcc0, ft0, ft1
58 bc1t fcc0, ${opcode}_finish
|
| OP_FLOAT_TO_INT.S | 37 c.ole.s fcc0, fa1, fa0
42 c.ole.s fcc0, fa0, fa1
47 c.un.s fcc0, fa0, fa1
|
| OP_FLOAT_TO_LONG.S | 39 c.ole.s fcc0, fa1, fa0
45 c.ole.s fcc0, fa0, fa1
51 c.un.s fcc0, fa0, fa1
|
| OP_DOUBLE_TO_LONG.S | 47 c.ole.d fcc0, fa1, fa0
54 c.ole.d fcc0, fa0, fa1
60 c.un.d fcc0, fa0, fa1
|
| binflop.S | 27 c.eq.s fcc0, ft0, fa1 # condition bit and comparision with 0
28 bc1t fcc0, common_errDivideByZero
|
| binflop2addr.S | 29 c.eq.s fcc0, ft0, fa1
30 bc1t fcc0, common_errDivideByZero
|
| OP_DOUBLE_TO_INT.S | 53 c.ole.d fcc0, fa1, fa0
59 c.ole.d fcc0, fa0, fa1
64 c.un.d fcc0, fa0, fa1
|
| binflopWide.S | 35 c.eq.d fcc0, fa1, ft0
36 bc1t fcc0, common_errDivideByZero
|
| binflopWide2addr.S | 29 c.eq.d fcc0, fa1, ft0
30 bc1t fcc0, common_errDivideByZero
|
| /external/llvm/test/CodeGen/SPARC/ |
| 2011-01-11-CC.ll | 72 ;V9: mov{{e|ne}} %fcc0
87 ;V9: fmovs{{e|ne}} %fcc0
101 ;V9: fmovd{{e|ne}} %fcc0
|
| 64cond.ll | 71 ; CHECK: movul %fcc0, %i2, %i3
|
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 248 // bc1t $fcc0, $L1 => bc1t $L1
249 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
251 // bc1f $fcc0, $L1 => bc1f $L1
252 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
|
| /dalvik/vm/compiler/template/out/ |
| CompilerTemplateAsm-mips.S | [all...] |
| /dalvik/vm/mterp/out/ |
| InterpAsm-mips.S | [all...] |
