| /art/compiler/dex/quick/mips/ |
| codegen_mips.h | 33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
38 int r_dest, int r_dest_hi, OpSize size, int s_reg);
41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
45 int r_src, int r_src_hi, OpSize size, int s_reg);
91 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
93 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
164 LIR* LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size,
166 LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size)
[all...] |
| utility_mips.cc | 337 int scale, OpSize size) {
389 int scale, OpSize size) {
435 int r_dest_hi, OpSize size, int s_reg) {
533 OpSize size, int s_reg) {
544 int r_src, int r_src_hi, OpSize size) {
626 OpSize size) {
646 int r_src, int r_src_hi, OpSize size, int s_reg) {
658 int r_dest, int r_dest_hi, OpSize size, int s_reg) {
|
| /art/compiler/dex/quick/arm/ |
| codegen_arm.h | 32 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
35 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37 int r_dest, int r_dest_hi, OpSize size, int s_reg);
40 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
42 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
44 int r_src, int r_src_hi, OpSize size, int s_reg);
90 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
92 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
164 LIR* LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size,
166 LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size)
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoderCommon.h | 79 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
87 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
89 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
100 ENUM_ENTRY(IC_64BIT_REXW_XS, 6, "OPSIZE could mean a different " \
110 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
114 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
118 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
122 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 4, "requires VEX, L, W and OpSize") \
126 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
130 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \
[all...] |
| /art/compiler/dex/quick/x86/ |
| codegen_x86.h | 33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
38 int r_dest, int r_dest_hi, OpSize size, int s_reg);
41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
45 int r_src, int r_src_hi, OpSize size, int s_reg);
91 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
93 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
|
| utility_x86.cc | 346 int displacement, int r_dest, int r_dest_hi, OpSize size,
446 int r_index, int r_dest, int scale, OpSize size) {
452 int r_dest, OpSize size, int s_reg) {
464 int displacement, int r_src, int r_src_hi, OpSize size,
545 int scale, OpSize size) {
551 int r_src, OpSize size) {
|
| /external/llvm/lib/Target/X86/ |
| X86InstrFormats.td | 115 class OpSize { bit hasOpSizePrefix = 1; }
367 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
377 let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
385 !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1]));
428 // PDI - SSE2 instructions with TB and OpSize prefixes, packed double domain.
429 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
431 // VPDI - SSE2 vector instructions with TB and OpSize prefixes in AVX form,
433 // VS2I - SSE2 scalar instructions with TB and OpSize prefixes in AVX form.
434 // S2I - SSE2 scalar instructions with TB and OpSize prefixes.
454 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
[all...] |
| X86InstrSystem.td | 67 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
83 "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize;
93 "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize;
103 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize;
113 "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize;
119 def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
170 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
177 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;
184 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;
191 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;
[all...] |
| X86InstrShiftRotate.td | 25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
42 OpSize;
58 "shl{w}\t$dst", [], IIC_SR>, OpSize;
78 OpSize;
94 OpSize;
113 OpSize;
131 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
146 IIC_SR>, OpSize;
161 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize;
179 OpSize;
[all...] |
| X86InstrVMX.td | 20 "invept\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
23 "invept\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
27 "invvpid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
30 "invvpid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
35 "vmclear\t$vmcs", []>, OpSize, TB;
|
| X86InstrControl.td | 29 [], IIC_RET>, OpSize;
35 [], IIC_RET_IMM>, OpSize;
39 "{l}ret{w|f}", [], IIC_RET>, OpSize;
45 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
129 IIC_JMP_FAR_PTR>, OpSize, Sched<[WriteJump]>;
139 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize,
179 IIC_CALL_FAR_PTR>, OpSize, Sched<[WriteJump]>;
186 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize,
196 "callw\t$dst", []>, OpSize;
|
| X86InstrExtension.td | 17 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
24 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
45 TB, OpSize, Sched<[WriteALU]>;
49 TB, OpSize, Sched<[WriteALULd]>;
71 TB, OpSize, Sched<[WriteALU]>;
75 TB, OpSize, Sched<[WriteALULd]>;
|
| X86InstrInfo.td | [all...] |
| X86InstrSSE.td | [all...] |
| X86InstrCMovSetCC.td | 25 IIC_CMOV16_RR>,TB,OpSize;
47 TB, OpSize;
|
| X86InstrArithmetic.td | 21 "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize;
71 [], IIC_MUL16_REG>, OpSize, Sched<[WriteIMul]>;
98 [], IIC_MUL16_MEM>, OpSize, SchedLoadReg<WriteIMulLd>;
118 IIC_IMUL16_RR>, OpSize, Sched<[WriteIMul]>;
136 "imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize,
160 TB, OpSize;
182 TB, OpSize;
211 IIC_IMUL16_RRI>, OpSize;
218 OpSize;
253 OpSize;
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| Codegen.h | 81 int displacement, int rSrc, OpSize size);
|
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 235 RegisterClass oat_reg_class_by_size(OpSize size) {
406 void GenIGet(uint32_t field_idx, int opt_flags, OpSize size,
408 void GenIPut(uint32_t field_idx, int opt_flags, OpSize size,
531 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0;
534 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0;
536 int r_dest, int r_dest_hi, OpSize size, int s_reg) = 0;
539 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0;
541 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0;
543 int r_src, int r_src_hi, OpSize size, int s_reg) = 0;
647 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array
[all...] |
| /dalvik/vm/compiler/codegen/ |
| Ralloc.h | 32 static inline RegisterClass dvmCompilerRegClassBySize(OpSize size)
222 int displacement, int rSrc, OpSize size);
|
| /external/llvm/utils/TableGen/ |
| DisassemblerEmitter.cpp | 38 /// instruction with an OPSIZE prefix and an XS prefix decodes the same way in
39 /// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix
|
| X86RecognizableInstr.h | 145 /// mandatory OpSize prefix.
149 /// @param hasOpSizePrefix Indicates whether the instruction has an OpSize
163 /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize
|
| /external/chromium_org/third_party/skia/src/core/ |
| SkPictureRecord.cpp | 70 static inline uint32_t getPaintOffset(DrawType op, uint32_t opSize) {
119 if (0 != (opSize & ~MASK_24) || opSize == MASK_24) {
129 if (kSaveLayerNoBoundsSize == opSize) {
132 SkASSERT(kSaveLayerWithBoundsSize == opSize);
476 uint32_t opSize;
477 DrawType op = peek_op_and_size(writer, offset, &opSize);
483 SkASSERT(kSaveSize == opSize);
485 // get the save flag (last 4-bytes of the space allocated for the opSize)
498 offset += opSize;
[all...] |
| /external/skia/src/core/ |
| SkPictureRecord.cpp | 70 static inline uint32_t getPaintOffset(DrawType op, uint32_t opSize) {
119 if (0 != (opSize & ~MASK_24) || opSize == MASK_24) {
129 if (kSaveLayerNoBoundsSize == opSize) {
132 SkASSERT(kSaveLayerWithBoundsSize == opSize);
476 uint32_t opSize;
477 DrawType op = peek_op_and_size(writer, offset, &opSize);
483 SkASSERT(kSaveSize == opSize);
485 // get the save flag (last 4-bytes of the space allocated for the opSize)
498 offset += opSize;
[all...] |
| /external/chromium_org/third_party/openssl/openssl/crypto/perlasm/ |
| x86gas.pl | 16 sub opsize() subroutine
42 if ($dst =~ m/^%/o) { $suffix=&opsize($dst); }
43 elsif ($src =~ m/^%/o) { $suffix=&opsize($src); }
|
| /external/openssl/crypto/perlasm/ |
| x86gas.pl | 16 sub opsize() subroutine
42 if ($dst =~ m/^%/o) { $suffix=&opsize($dst); }
43 elsif ($src =~ m/^%/o) { $suffix=&opsize($src); }
|
