| /external/llvm/lib/Target/Sparc/ |
| SparcInstr64Bit.td | 64 // The ALU instructions want their simm13 operands as i32 immediates.
68 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
98 // (sllx simm13, n)
102 // (xor (sllx sethi), simm13)
103 // (sllx (xor sethi, simm13))
112 // (or (sllx sethi), (or sethi, simm13))
113 // (xnor (sllx sethi), (or sethi, simm13))
119 // (or (sllx (or sethi, simmm13)), (or sethi, simm13))
167 def : Pat<(and i64:$a, (i64 simm13:$b)), (ANDri $a, (as_i32imm $b))>;
168 def : Pat<(or i64:$a, (i64 simm13:$b)), (ORri $a, (as_i32imm $b))>
[all...] |
| SparcInstrFormats.td | 94 bits<13> simm13;
100 let Inst{12-0} = simm13;
|
| SparcInstrInfo.td | 54 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
198 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>;
239 let rd = 0, rs1 = 1, simm13 = 3 in
291 "jmp %o7+$val", [(retflag simm13:$val)]>;
478 [(SPcmpicc i32:$b, (i32 simm13:$c))]>;
791 def : Pat<(i32 simm13:$val),
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_arm_defs.h | 133 Int simm13; /* -4095 .. +4095 */ member in struct:__anon27157::__anon27158::__anon27159
144 extern ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 );
|
| host_arm_defs.c | 219 ARMAMode1* ARMAMode1_RI ( HReg reg, Int simm13 ) {
223 am->ARMam1.RI.simm13 = simm13;
224 vassert(-4095 <= simm13 && simm13 <= 4095);
240 vex_printf("%d(", am->ARMam1.RI.simm13);
[all...] |
| host_arm_isel.c | 657 && am->ARMam1.RI.simm13 >= -4095
658 && am->ARMam1.RI.simm13 <= 4095 );
686 /* {Add32,Sub32}(expr,simm13) */
[all...] |
| /external/llvm/docs/ |
| WritingAnLLVMBackend.rst | [all...] |
