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  /external/llvm/test/CodeGen/Mips/
setgek.ll 14 ; 16: slti ${{[0-9]+}}, -32768
setltk.ll 17 ; 16: slti $[[REGISTER:[0-9]+]], 10
selTBtnezSlti.ll 22 ; 16: slti ${{[0-9]+}}, 10
selgek.ll 82 ; 16: slti ${{[0-9]+}}, 1000
85 ; 16: slti ${{[0-9]+}}, 1 # 16 bit inst
88 ; 16: slti ${{[0-9]+}}, 2 # 16 bit inst
91 ; 16: slti ${{[0-9]+}}, 2 # 16 bit inst
cmov.ll 62 ; slti and conditional move.
71 ; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
92 ; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
115 ; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
136 ; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
selltk.ll 88 ; 16: slti ${{[0-9]+}}, 3 # 16 bit inst
91 ; 16: slti ${{[0-9]+}}, 3 # 16 bit inst
setcc-se.ll 26 ; CHECK: slti $[[R0:[0-9]+]], $4, -32768
59 ; CHECK: slti $[[R0:[0-9]+]], $4, 32767
  /external/chromium_org/v8/test/cctest/
test-disasm-mips.cc 355 COMPARE(slti(a0, a1, 0),
356 "28a40000 slti a0, a1, 0");
357 COMPARE(slti(s0, s1, 32767),
358 "2a307fff slti s0, s1, 32767");
359 COMPARE(slti(t2, t3, -32768),
360 "296a8000 slti t2, t3, -32768");
361 COMPARE(slti(v0, v1, -1),
362 "2862ffff slti v0, v1, -1");
  /external/v8/test/cctest/
test-disasm-mips.cc 365 COMPARE(slti(a0, a1, 0),
366 "28a40000 slti a0, a1, 0");
367 COMPARE(slti(s0, s1, 32767),
368 "2a307fff slti s0, s1, 32767");
369 COMPARE(slti(t2, t3, -32768),
370 "296a8000 slti t2, t3, -32768");
371 COMPARE(slti(v0, v1, -1),
372 "2862ffff slti v0, v1, -1");
  /external/llvm/test/MC/Mips/
micromips-alu-instructions.s 19 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x90]
20 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x90]
49 slti $3, $3, 103
mips-alu-instructions.s 24 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
25 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
56 slti $3, $3, 103
mips64-alu-instructions.s 22 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
23 # CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
51 slti $3, $3, 103
  /external/llvm/lib/Target/Mips/
MipsCondMov.td 195 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
199 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
219 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
230 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
235 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
MicroMipsInstrInfo.td 7 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
Mips16InstrInfo.td 397 // op2 can be cmpi or slti/sltiu
607 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
629 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
990 // Purpose: b = Slti rl, imm.
994 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
1045 // Purpose: b = Slti rl, imm.
1049 def SelTBtneZSlti: SeliT<"btnez", "slti">;
1061 // Purpose: b = Slti rl, imm.
1089 // Format: SLTI rx, immediate MIPS16e
1094 def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu>
    [all...]
  /system/core/libcutils/tests/memset_mips/
memset_omips.S 38 slti t1, a2, 8 # Less than 8?
memset_cmips.S 68 slti AT,a2,4 # is a2 less than 4?
  /bionic/libc/arch-mips/string/
memset.S 108 slti t1,a2,4 # .Laligned for 4 or more bytes
156 slti AT,a2,4 # is a2 less than 4?
  /external/valgrind/main/none/tests/mips32/
MIPS32int.c     [all...]
MIPS32int.stdout.exp     [all...]
MIPS32int.stdout.exp-BE     [all...]
MIPS32int.stdout.exp-mips32     [all...]
  /art/compiler/dex/quick/mips/
int_mips.cc 135 // TUNING: handle s16 & kCondLt/Mi case using slti
152 // Tuning: use slti when applicable
  /external/chromium_org/v8/src/mips/
constants-mips.cc 319 case SLTI:
  /external/v8/src/mips/
constants-mips.cc 313 case SLTI:

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