1 //===--- arm_neon.td - ARM NEON compiler interface ------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the TableGen definitions from which the ARM NEON header 11 // file will be generated. See ARM document DUI0348B. 12 // 13 //===----------------------------------------------------------------------===// 14 15 class Op; 16 17 def OP_NONE : Op; 18 def OP_UNAVAILABLE : Op; 19 def OP_ADD : Op; 20 def OP_ADDL : Op; 21 def OP_ADDW : Op; 22 def OP_SUB : Op; 23 def OP_SUBL : Op; 24 def OP_SUBW : Op; 25 def OP_MUL : Op; 26 def OP_MLA : Op; 27 def OP_MLAL : Op; 28 def OP_MLS : Op; 29 def OP_MLSL : Op; 30 def OP_MUL_N : Op; 31 def OP_MLA_N : Op; 32 def OP_MLS_N : Op; 33 def OP_MLAL_N : Op; 34 def OP_MLSL_N : Op; 35 def OP_MUL_LN: Op; 36 def OP_MULL_LN : Op; 37 def OP_MLA_LN: Op; 38 def OP_MLS_LN: Op; 39 def OP_MLAL_LN : Op; 40 def OP_MLSL_LN : Op; 41 def OP_QDMULL_LN : Op; 42 def OP_QDMLAL_LN : Op; 43 def OP_QDMLSL_LN : Op; 44 def OP_QDMULH_LN : Op; 45 def OP_QRDMULH_LN : Op; 46 def OP_EQ : Op; 47 def OP_GE : Op; 48 def OP_LE : Op; 49 def OP_GT : Op; 50 def OP_LT : Op; 51 def OP_NEG : Op; 52 def OP_NOT : Op; 53 def OP_AND : Op; 54 def OP_OR : Op; 55 def OP_XOR : Op; 56 def OP_ANDN : Op; 57 def OP_ORN : Op; 58 def OP_CAST : Op; 59 def OP_HI : Op; 60 def OP_LO : Op; 61 def OP_CONC : Op; 62 def OP_DUP : Op; 63 def OP_DUP_LN: Op; 64 def OP_SEL : Op; 65 def OP_REV64 : Op; 66 def OP_REV32 : Op; 67 def OP_REV16 : Op; 68 def OP_REINT : Op; 69 def OP_ABDL : Op; 70 def OP_ABA : Op; 71 def OP_ABAL : Op; 72 def OP_DIV : Op; 73 74 class Inst <string n, string p, string t, Op o> { 75 string Name = n; 76 string Prototype = p; 77 string Types = t; 78 Op Operand = o; 79 bit isShift = 0; 80 bit isVCVT_N = 0; 81 bit isA64 = 0; 82 83 // Certain intrinsics have different names than their representative 84 // instructions. This field allows us to handle this correctly when we 85 // are generating tests. 86 string InstName = ""; 87 88 // Certain intrinsics even though they are not a WOpInst or LOpInst, 89 // generate a WOpInst/LOpInst instruction (see below for definition 90 // of a WOpInst/LOpInst). For testing purposes we need to know 91 // this. Ex: vset_lane which outputs vmov instructions. 92 bit isHiddenWInst = 0; 93 bit isHiddenLInst = 0; 94 } 95 96 // The following instruction classes are implemented via builtins. 97 // These declarations are used to generate Builtins.def: 98 // 99 // SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8") 100 // IInst: Instruction with generic integer suffix (e.g., "i8") 101 // WInst: Instruction with only bit size suffix (e.g., "8") 102 class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 103 class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 104 class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 105 106 // The following instruction classes are implemented via operators 107 // instead of builtins. As such these declarations are only used for 108 // the purpose of generating tests. 109 // 110 // SOpInst: Instruction with signed/unsigned suffix (e.g., "s8", 111 // "u8", "p8"). 112 // IOpInst: Instruction with generic integer suffix (e.g., "i8"). 113 // WOpInst: Instruction with bit size only suffix (e.g., "8"). 114 // LOpInst: Logical instruction with no bit size suffix. 115 // NoTestOpInst: Intrinsic that has no corresponding instruction. 116 class SOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 117 class IOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 118 class WOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 119 class LOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 120 class NoTestOpInst<string n, string p, string t, Op o> : Inst<n, p, t, o> {} 121 122 // prototype: return (arg, arg, ...) 123 // v: void 124 // t: best-fit integer (int/poly args) 125 // x: signed integer (int/float args) 126 // u: unsigned integer (int/float args) 127 // f: float (int args) 128 // d: default 129 // g: default, ignore 'Q' size modifier. 130 // w: double width elements, same num elts 131 // n: double width elements, half num elts 132 // h: half width elements, double num elts 133 // e: half width elements, double num elts, unsigned 134 // i: constant int 135 // l: constant uint64 136 // s: scalar of element type 137 // a: scalar of element type (splat to vector type) 138 // k: default elt width, double num elts 139 // #: array of default vectors 140 // p: pointer type 141 // c: const pointer type 142 143 // sizes: 144 // c: char 145 // s: short 146 // i: int 147 // l: long 148 // f: float 149 // h: half-float 150 // d: double 151 152 // size modifiers: 153 // U: unsigned 154 // Q: 128b 155 // P: polynomial 156 157 //////////////////////////////////////////////////////////////////////////////// 158 // E.3.1 Addition 159 def VADD : IOpInst<"vadd", "ddd", 160 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>; 161 def VADDL : SOpInst<"vaddl", "wdd", "csiUcUsUi", OP_ADDL>; 162 def VADDW : SOpInst<"vaddw", "wwd", "csiUcUsUi", OP_ADDW>; 163 def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 164 def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 165 def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 166 def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">; 167 def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">; 168 169 //////////////////////////////////////////////////////////////////////////////// 170 // E.3.2 Multiplication 171 def VMUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>; 172 def VMULP : SInst<"vmul", "ddd", "PcQPc">; 173 def VMLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>; 174 def VMLAL : SOpInst<"vmlal", "wwdd", "csiUcUsUi", OP_MLAL>; 175 def VMLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>; 176 def VMLSL : SOpInst<"vmlsl", "wwdd", "csiUcUsUi", OP_MLSL>; 177 def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">; 178 def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">; 179 def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">; 180 def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">; 181 def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">; 182 def VQDMULL : SInst<"vqdmull", "wdd", "si">; 183 184 //////////////////////////////////////////////////////////////////////////////// 185 // E.3.3 Subtraction 186 def VSUB : IOpInst<"vsub", "ddd", 187 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>; 188 def VSUBL : SOpInst<"vsubl", "wdd", "csiUcUsUi", OP_SUBL>; 189 def VSUBW : SOpInst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>; 190 def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 191 def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 192 def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">; 193 def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">; 194 195 //////////////////////////////////////////////////////////////////////////////// 196 // E.3.4 Comparison 197 def VCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>; 198 def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>; 199 let InstName = "vcge" in 200 def VCLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>; 201 def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>; 202 let InstName = "vcgt" in 203 def VCLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>; 204 let InstName = "vacge" in { 205 def VCAGE : IInst<"vcage", "udd", "fQf">; 206 def VCALE : IInst<"vcale", "udd", "fQf">; 207 } 208 let InstName = "vacgt" in { 209 def VCAGT : IInst<"vcagt", "udd", "fQf">; 210 def VCALT : IInst<"vcalt", "udd", "fQf">; 211 } 212 def VTST : WInst<"vtst", "udd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc">; 213 214 //////////////////////////////////////////////////////////////////////////////// 215 // E.3.5 Absolute Difference 216 def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 217 def VABDL : SOpInst<"vabdl", "wdd", "csiUcUsUi", OP_ABDL>; 218 def VABA : SOpInst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>; 219 def VABAL : SOpInst<"vabal", "wwdd", "csiUcUsUi", OP_ABAL>; 220 221 //////////////////////////////////////////////////////////////////////////////// 222 // E.3.6 Max/Min 223 def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 224 def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 225 226 //////////////////////////////////////////////////////////////////////////////// 227 // E.3.7 Pairwise Addition 228 def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">; 229 def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">; 230 def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">; 231 232 //////////////////////////////////////////////////////////////////////////////// 233 // E.3.8-9 Folding Max/Min 234 def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">; 235 def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">; 236 237 //////////////////////////////////////////////////////////////////////////////// 238 // E.3.10 Reciprocal/Sqrt 239 def VRECPS : IInst<"vrecps", "ddd", "fQf">; 240 def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">; 241 242 //////////////////////////////////////////////////////////////////////////////// 243 // E.3.11 Shifts by signed variable 244 def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 245 def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 246 def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 247 def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 248 249 //////////////////////////////////////////////////////////////////////////////// 250 // E.3.12 Shifts by constant 251 let isShift = 1 in { 252 def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 253 def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 254 def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 255 def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 256 def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 257 def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 258 def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">; 259 def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">; 260 def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">; 261 def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">; 262 def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">; 263 def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">; 264 def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">; 265 def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">; 266 267 //////////////////////////////////////////////////////////////////////////////// 268 // E.3.13 Shifts with insert 269 def VSRI_N : WInst<"vsri_n", "dddi", 270 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 271 def VSLI_N : WInst<"vsli_n", "dddi", 272 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 273 } 274 275 //////////////////////////////////////////////////////////////////////////////// 276 // E.3.14 Loads and stores of a single vector 277 def VLD1 : WInst<"vld1", "dc", 278 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 279 def VLD1_LANE : WInst<"vld1_lane", "dcdi", 280 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 281 def VLD1_DUP : WInst<"vld1_dup", "dc", 282 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 283 def VST1 : WInst<"vst1", "vpd", 284 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 285 def VST1_LANE : WInst<"vst1_lane", "vpdi", 286 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 287 288 //////////////////////////////////////////////////////////////////////////////// 289 // E.3.15 Loads and stores of an N-element structure 290 def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 291 def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 292 def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 293 def VLD2_DUP : WInst<"vld2_dup", "2c", "UcUsUiUlcsilhfPcPs">; 294 def VLD3_DUP : WInst<"vld3_dup", "3c", "UcUsUiUlcsilhfPcPs">; 295 def VLD4_DUP : WInst<"vld4_dup", "4c", "UcUsUiUlcsilhfPcPs">; 296 def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 297 def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 298 def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 299 def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 300 def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 301 def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 302 def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 303 def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 304 def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 305 306 //////////////////////////////////////////////////////////////////////////////// 307 // E.3.16 Extract lanes from a vector 308 let InstName = "vmov" in 309 def VGET_LANE : IInst<"vget_lane", "sdi", 310 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 311 312 //////////////////////////////////////////////////////////////////////////////// 313 // E.3.17 Set lanes within a vector 314 let InstName = "vmov" in 315 def VSET_LANE : IInst<"vset_lane", "dsdi", 316 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 317 318 //////////////////////////////////////////////////////////////////////////////// 319 // E.3.18 Initialize a vector from bit pattern 320 def VCREATE : NoTestOpInst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST>; 321 322 //////////////////////////////////////////////////////////////////////////////// 323 // E.3.19 Set all lanes to same value 324 let InstName = "vmov" in { 325 def VDUP_N : WOpInst<"vdup_n", "ds", 326 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>; 327 def VMOV_N : WOpInst<"vmov_n", "ds", 328 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", OP_DUP>; 329 } 330 let InstName = "" in 331 def VDUP_LANE: WOpInst<"vdup_lane", "dgi", 332 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", 333 OP_DUP_LN>; 334 335 //////////////////////////////////////////////////////////////////////////////// 336 // E.3.20 Combining vectors 337 def VCOMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>; 338 339 //////////////////////////////////////////////////////////////////////////////// 340 // E.3.21 Splitting vectors 341 let InstName = "vmov" in { 342 def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>; 343 def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>; 344 } 345 346 //////////////////////////////////////////////////////////////////////////////// 347 // E.3.22 Converting vectors 348 def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">; 349 def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">; 350 def VCVT_F16 : SInst<"vcvt_f16", "hk", "f">; 351 def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">; 352 def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "fd", "h">; 353 let isVCVT_N = 1 in { 354 def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">; 355 def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">; 356 def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">; 357 } 358 def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">; 359 def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">; 360 def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">; 361 def VQMOVUN : SInst<"vqmovun", "ek", "sil">; 362 363 //////////////////////////////////////////////////////////////////////////////// 364 // E.3.23-24 Table lookup, Extended table lookup 365 let InstName = "vtbl" in { 366 def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">; 367 def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">; 368 def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">; 369 def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">; 370 } 371 let InstName = "vtbx" in { 372 def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">; 373 def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">; 374 def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">; 375 def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">; 376 } 377 378 //////////////////////////////////////////////////////////////////////////////// 379 // E.3.25 Operations with a scalar value 380 def VMLA_LANE : IOpInst<"vmla_lane", "dddgi", 381 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 382 def VMLAL_LANE : SOpInst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>; 383 def VQDMLAL_LANE : SOpInst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>; 384 def VMLS_LANE : IOpInst<"vmls_lane", "dddgi", 385 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 386 def VMLSL_LANE : SOpInst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>; 387 def VQDMLSL_LANE : SOpInst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>; 388 def VMUL_N : IOpInst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>; 389 def VMUL_LANE : IOpInst<"vmul_lane", "ddgi", 390 "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>; 391 def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">; 392 def VMULL_LANE : SOpInst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>; 393 def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">; 394 def VQDMULL_LANE : SOpInst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>; 395 def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">; 396 def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>; 397 def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">; 398 def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>; 399 def VMLA_N : IOpInst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>; 400 def VMLAL_N : SOpInst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>; 401 def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">; 402 def VMLS_N : IOpInst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>; 403 def VMLSL_N : SOpInst<"vmlsl_n", "wwda", "siUsUi", OP_MLSL_N>; 404 def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">; 405 406 //////////////////////////////////////////////////////////////////////////////// 407 // E.3.26 Vector Extract 408 def VEXT : WInst<"vext", "dddi", 409 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">; 410 411 //////////////////////////////////////////////////////////////////////////////// 412 // E.3.27 Reverse vector elements 413 def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", 414 OP_REV64>; 415 def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>; 416 def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>; 417 418 //////////////////////////////////////////////////////////////////////////////// 419 // E.3.28 Other single operand arithmetic 420 def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">; 421 def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">; 422 def VNEG : SOpInst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>; 423 def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">; 424 def VCLS : SInst<"vcls", "dd", "csiQcQsQi">; 425 def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">; 426 def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">; 427 def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">; 428 def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">; 429 430 //////////////////////////////////////////////////////////////////////////////// 431 // E.3.29 Logical operations 432 def VMVN : LOpInst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>; 433 def VAND : LOpInst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>; 434 def VORR : LOpInst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>; 435 def VEOR : LOpInst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>; 436 def VBIC : LOpInst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>; 437 def VORN : LOpInst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>; 438 let isHiddenLInst = 1 in 439 def VBSL : SInst<"vbsl", "dudd", 440 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">; 441 442 //////////////////////////////////////////////////////////////////////////////// 443 // E.3.30 Transposition operations 444 def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 445 def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 446 def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 447 448 //////////////////////////////////////////////////////////////////////////////// 449 // E.3.31 Vector reinterpret cast operations 450 def VREINTERPRET 451 : NoTestOpInst<"vreinterpret", "dd", 452 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT>; 453 454 //////////////////////////////////////////////////////////////////////////////// 455 // Vector fused multiply-add operations 456 457 def VFMA : SInst<"vfma", "dddd", "fQf">; 458 459 //////////////////////////////////////////////////////////////////////////////// 460 // AArch64 Intrinsics 461 462 let isA64 = 1 in { 463 464 //////////////////////////////////////////////////////////////////////////////// 465 // Addition 466 // With additional Qd type. 467 def ADD : IOpInst<"vadd", "ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUlQd", OP_ADD>; 468 469 //////////////////////////////////////////////////////////////////////////////// 470 // Subtraction 471 // With additional Qd type. 472 def SUB : IOpInst<"vsub", "ddd", "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUlQd", OP_SUB>; 473 474 //////////////////////////////////////////////////////////////////////////////// 475 // Multiplication 476 // With additional Qd type. 477 def MUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MUL>; 478 def MLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLA>; 479 def MLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUiQd", OP_MLS>; 480 481 //////////////////////////////////////////////////////////////////////////////// 482 // Multiplication Extended 483 def MULX : SInst<"vmulx", "ddd", "fQfQd">; 484 485 //////////////////////////////////////////////////////////////////////////////// 486 // Division 487 def FDIV : IOpInst<"vdiv", "ddd", "fQfQd", OP_DIV>; 488 489 //////////////////////////////////////////////////////////////////////////////// 490 // Vector fused multiply-add operations 491 // With additional Qd type. 492 def FMLA : SInst<"vfma", "dddd", "fQfQd">; 493 def FMLS : SInst<"vfms", "dddd", "fQfQd">; 494 495 //////////////////////////////////////////////////////////////////////////////// 496 // Logical operations 497 // With additional Qd type. 498 def BSL : SInst<"vbsl", "dudd", "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPsQd">; 499 500 //////////////////////////////////////////////////////////////////////////////// 501 // Absolute Difference 502 // With additional Qd type. 503 def ABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 504 505 //////////////////////////////////////////////////////////////////////////////// 506 // Reciprocal/Sqrt 507 // With additional Qd type. 508 def FRECPS : IInst<"vrecps", "ddd", "fQfQd">; 509 def FRSQRTS : IInst<"vrsqrts", "ddd", "fQfQd">; 510 511 //////////////////////////////////////////////////////////////////////////////// 512 // Comparison 513 // With additional Qd type. 514 def FCAGE : IInst<"vcage", "udd", "fQfQd">; 515 def FCAGT : IInst<"vcagt", "udd", "fQfQd">; 516 def FCALE : IInst<"vcale", "udd", "fQfQd">; 517 def FCALT : IInst<"vcalt", "udd", "fQfQd">; 518 // With additional Ql, QUl, Qd types. 519 def CMTST : WInst<"vtst", "udd", "csiUcUsUiPcQcQsQiQlQUcQUsQUiQUlQPc">; 520 def CFMEQ : SOpInst<"vceq", "udd", 521 "csifUcUsUiPcQcQsQiQlQfQUcQUsQUiQUlQPcQd", OP_EQ>; 522 def CFMGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_GE>; 523 def CFMLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_LE>; 524 def CFMGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_GT>; 525 def CFMLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_LT>; 526 527 //////////////////////////////////////////////////////////////////////////////// 528 // Max/Min Integer 529 // With additional Qd type. 530 def MAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 531 def MIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 532 533 //////////////////////////////////////////////////////////////////////////////// 534 // MaxNum/MinNum Floating Point 535 def FMAXNM : SInst<"vmaxnm", "ddd", "fQfQd">; 536 def FMINNM : SInst<"vminnm", "ddd", "fQfQd">; 537 538 //////////////////////////////////////////////////////////////////////////////// 539 // Pairwise Max/Min 540 // With additional Qc Qs Qi QUc QUs QUi Qf Qd types. 541 def MAXP : SInst<"vpmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 542 def MINP : SInst<"vpmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 543 544 //////////////////////////////////////////////////////////////////////////////// 545 // Pairwise MaxNum/MinNum Floating Point 546 def FMAXNMP : SInst<"vpmaxnm", "ddd", "fQfQd">; 547 def FMINNMP : SInst<"vpminnm", "ddd", "fQfQd">; 548 549 //////////////////////////////////////////////////////////////////////////////// 550 // Pairwise Addition 551 // With additional Qc Qs Qi QUc QUs QUi Qf Qd types. 552 def ADDP : IInst<"vpadd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQfQd">; 553 554 //////////////////////////////////////////////////////////////////////////////// 555 // Scalar Arithmetic 556 557 // Scalar Addition 558 559 def SCALAR_ADD : Inst<"vaddd", "ddd", "lUl", OP_ADD>; 560 561 // Scalar Subtraction 562 def SCALAR_SUB : Inst<"vsubd", "ddd", "lUl", OP_SUB>; 563 564 } 565
