1 llc - LLVM static compiler 2 ========================== 3 4 SYNOPSIS 5 -------- 6 7 :program:`llc` [*options*] [*filename*] 8 9 DESCRIPTION 10 ----------- 11 12 The :program:`llc` command compiles LLVM source inputs into assembly language 13 for a specified architecture. The assembly language output can then be passed 14 through a native assembler and linker to generate a native executable. 15 16 The choice of architecture for the output assembly code is automatically 17 determined from the input file, unless the :option:`-march` option is used to 18 override the default. 19 20 OPTIONS 21 ------- 22 23 If ``filename`` is "``-``" or omitted, :program:`llc` reads from standard input. 24 Otherwise, it will from ``filename``. Inputs can be in either the LLVM assembly 25 language format (``.ll``) or the LLVM bitcode format (``.bc``). 26 27 If the :option:`-o` option is omitted, then :program:`llc` will send its output 28 to standard output if the input is from standard input. If the :option:`-o` 29 option specifies "``-``", then the output will also be sent to standard output. 30 31 If no :option:`-o` option is specified and an input file other than "``-``" is 32 specified, then :program:`llc` creates the output filename by taking the input 33 filename, removing any existing ``.bc`` extension, and adding a ``.s`` suffix. 34 35 Other :program:`llc` options are described below. 36 37 End-user Options 38 ~~~~~~~~~~~~~~~~ 39 40 .. option:: -help 41 42 Print a summary of command line options. 43 44 .. option:: -O=uint 45 46 Generate code at different optimization levels. These correspond to the 47 ``-O0``, ``-O1``, ``-O2``, and ``-O3`` optimization levels used by 48 :program:`llvm-gcc` and :program:`clang`. 49 50 .. option:: -mtriple=<target triple> 51 52 Override the target triple specified in the input file with the specified 53 string. 54 55 .. option:: -march=<arch> 56 57 Specify the architecture for which to generate assembly, overriding the target 58 encoded in the input file. See the output of ``llc -help`` for a list of 59 valid architectures. By default this is inferred from the target triple or 60 autodetected to the current architecture. 61 62 .. option:: -mcpu=<cpuname> 63 64 Specify a specific chip in the current architecture to generate code for. 65 By default this is inferred from the target triple and autodetected to 66 the current architecture. For a list of available CPUs, use: 67 68 .. code-block:: none 69 70 llvm-as < /dev/null | llc -march=xyz -mcpu=help 71 72 .. option:: -filetype=<output file type> 73 74 Specify what kind of output ``llc`` should generated. Options are: ``asm`` 75 for textual assembly ( ``'.s'``), ``obj`` for native object files (``'.o'``) 76 and ``null`` for not emitting anything (for performance testing). 77 78 Note that not all targets support all options. 79 80 .. option:: -mattr=a1,+a2,-a3,... 81 82 Override or control specific attributes of the target, such as whether SIMD 83 operations are enabled or not. The default set of attributes is set by the 84 current CPU. For a list of available attributes, use: 85 86 .. code-block:: none 87 88 llvm-as < /dev/null | llc -march=xyz -mattr=help 89 90 .. option:: --disable-fp-elim 91 92 Disable frame pointer elimination optimization. 93 94 .. option:: --disable-excess-fp-precision 95 96 Disable optimizations that may produce excess precision for floating point. 97 Note that this option can dramatically slow down code on some systems 98 (e.g. X86). 99 100 .. option:: --enable-no-infs-fp-math 101 102 Enable optimizations that assume no Inf values. 103 104 .. option:: --enable-no-nans-fp-math 105 106 Enable optimizations that assume no NAN values. 107 108 .. option:: --enable-unsafe-fp-math 109 110 Enable optimizations that make unsafe assumptions about IEEE math (e.g. that 111 addition is associative) or may not work for all input ranges. These 112 optimizations allow the code generator to make use of some instructions which 113 would otherwise not be usable (such as ``fsin`` on X86). 114 115 .. option:: --enable-correct-eh-support 116 117 Instruct the **lowerinvoke** pass to insert code for correct exception 118 handling support. This is expensive and is by default omitted for efficiency. 119 120 .. option:: --stats 121 122 Print statistics recorded by code-generation passes. 123 124 .. option:: --time-passes 125 126 Record the amount of time needed for each pass and print a report to standard 127 error. 128 129 .. option:: --load=<dso_path> 130 131 Dynamically load ``dso_path`` (a path to a dynamically shared object) that 132 implements an LLVM target. This will permit the target name to be used with 133 the :option:`-march` option so that code can be generated for that target. 134 135 Tuning/Configuration Options 136 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 137 138 .. option:: --print-machineinstrs 139 140 Print generated machine code between compilation phases (useful for debugging). 141 142 .. option:: --regalloc=<allocator> 143 144 Specify the register allocator to use. 145 Valid register allocators are: 146 147 *basic* 148 149 Basic register allocator. 150 151 *fast* 152 153 Fast register allocator. It is the default for unoptimized code. 154 155 *greedy* 156 157 Greedy register allocator. It is the default for optimized code. 158 159 *pbqp* 160 161 Register allocator based on 'Partitioned Boolean Quadratic Programming'. 162 163 .. option:: --spiller=<spiller> 164 165 Specify the spiller to use for register allocators that support it. Currently 166 this option is used only by the linear scan register allocator. The default 167 ``spiller`` is *local*. Valid spillers are: 168 169 *simple* 170 171 Simple spiller 172 173 *local* 174 175 Local spiller 176 177 Intel IA-32-specific Options 178 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 179 180 .. option:: --x86-asm-syntax=[att|intel] 181 182 Specify whether to emit assembly code in AT&T syntax (the default) or Intel 183 syntax. 184 185 EXIT STATUS 186 ----------- 187 188 If :program:`llc` succeeds, it will exit with 0. Otherwise, if an error 189 occurs, it will exit with a non-zero value. 190 191 SEE ALSO 192 -------- 193 194 lli 195 196
