1 //=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 // There are four SLOTS (four parallel pipelines) in Hexagon V4 machine. 11 // This file describes that machine information. 12 13 // 14 // |===========|==================================================| 15 // | PIPELINE | Instruction Classes | 16 // |===========|==================================================| 17 // | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM | 18 // |-----------|--------------------------------------------------| 19 // | SLOT1 | LD ST ALU32 | 20 // |-----------|--------------------------------------------------| 21 // | SLOT2 | XTYPE ALU32 J JR | 22 // |-----------|--------------------------------------------------| 23 // | SLOT3 | XTYPE ALU32 J CR | 24 // |===========|==================================================| 25 26 // Functional Units. 27 def SLOT0 : FuncUnit; 28 def SLOT1 : FuncUnit; 29 def SLOT2 : FuncUnit; 30 def SLOT3 : FuncUnit; 31 // Endloop is a pseudo instruction that is encoded with 2 bits in a packet 32 // rather than taking an execution slot. This special unit is needed 33 // to schedule an ENDLOOP with 4 other instructions. 34 def SLOT_ENDLOOP: FuncUnit; 35 36 // Itinerary classes. 37 def NV_V4 : InstrItinClass; 38 def MEM_V4 : InstrItinClass; 39 // ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4. 40 def PREFIX : InstrItinClass; 41 42 def HexagonItinerariesV4 : 43 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [ 44 InstrItinData<ALU32 , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 45 InstrItinData<ALU64 , [InstrStage<1, [SLOT2, SLOT3]>]>, 46 InstrItinData<CR , [InstrStage<1, [SLOT3]>]>, 47 InstrItinData<J , [InstrStage<1, [SLOT2, SLOT3]>]>, 48 InstrItinData<JR , [InstrStage<1, [SLOT2]>]>, 49 InstrItinData<LD , [InstrStage<1, [SLOT0, SLOT1]>]>, 50 InstrItinData<LD0 , [InstrStage<1, [SLOT0]>]>, 51 InstrItinData<M , [InstrStage<1, [SLOT2, SLOT3]>]>, 52 InstrItinData<ST , [InstrStage<1, [SLOT0, SLOT1]>]>, 53 InstrItinData<ST0 , [InstrStage<1, [SLOT0]>]>, 54 InstrItinData<S , [InstrStage<1, [SLOT2, SLOT3]>]>, 55 InstrItinData<SYS , [InstrStage<1, [SLOT0]>]>, 56 InstrItinData<NV_V4 , [InstrStage<1, [SLOT0]>]>, 57 InstrItinData<MEM_V4 , [InstrStage<1, [SLOT0]>]>, 58 InstrItinData<ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]>, 59 InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 60 InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 61 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, 62 InstrStage<1, [SLOT2, SLOT3]>]> 63 ]>; 64 65 def HexagonModelV4 : SchedMachineModel { 66 // Max issue per cycle == bundle width. 67 let IssueWidth = 4; 68 let Itineraries = HexagonItinerariesV4; 69 let LoadLatency = 1; 70 } 71 72 //===----------------------------------------------------------------------===// 73 // Hexagon V4 Resource Definitions - 74 //===----------------------------------------------------------------------===// 75
