1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This is the top level entry point for the PowerPC target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // Get the target-independent interfaces which we are implementing. 15 // 16 include "llvm/Target/Target.td" 17 18 //===----------------------------------------------------------------------===// 19 // PowerPC Subtarget features. 20 // 21 22 //===----------------------------------------------------------------------===// 23 // CPU Directives // 24 //===----------------------------------------------------------------------===// 25 26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">; 27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">; 28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">; 29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; 32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; 33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; 34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; 35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; 36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; 37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; 38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective", 39 "PPC::DIR_E500mc", "">; 40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective", 41 "PPC::DIR_E5500", "">; 42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">; 43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">; 44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">; 45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">; 46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">; 47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">; 48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; 49 50 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 51 "Enable 64-bit instructions">; 52 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 53 "Enable 64-bit registers usage for ppc32 [beta]">; 54 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 55 "Enable Altivec instructions">; 56 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 57 "Enable the MFOCRF instruction">; 58 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 59 "Enable the fsqrt instruction">; 60 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 61 "Enable the fre instruction">; 62 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 63 "Enable the fres instruction">; 64 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 65 "Enable the frsqrte instruction">; 66 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 67 "Enable the frsqrtes instruction">; 68 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 69 "Assume higher precision reciprocal estimates">; 70 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 71 "Enable the stfiwx instruction">; 72 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 73 "Enable the lfiwax instruction">; 74 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 75 "Enable the fri[mnpz] instructions">; 76 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 77 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">; 78 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 79 "Enable the isel instruction">; 80 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true", 81 "Enable the popcnt[dw] instructions">; 82 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 83 "Enable the ldbrx instruction">; 84 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 85 "Enable Book E instructions">; 86 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", 87 "Enable QPX instructions">; 88 89 // Note: Future features to add when support is extended to more 90 // recent ISA levels: 91 // 92 // CMPB p6, p6x, p7 cmpb 93 // DFP p6, p6x, p7 decimal floating-point instructions 94 // POPCNTB p5 through p7 popcntb and related instructions 95 // VSX p7 vector-scalar instruction set 96 97 //===----------------------------------------------------------------------===// 98 // Classes used for relation maps. 99 //===----------------------------------------------------------------------===// 100 // RecFormRel - Filter class used to relate non-record-form instructions with 101 // their record-form variants. 102 class RecFormRel; 103 104 //===----------------------------------------------------------------------===// 105 // Relation Map Definitions. 106 //===----------------------------------------------------------------------===// 107 108 def getRecordFormOpcode : InstrMapping { 109 let FilterClass = "RecFormRel"; 110 // Instructions with the same BaseName and Interpretation64Bit values 111 // form a row. 112 let RowFields = ["BaseName", "Interpretation64Bit"]; 113 // Instructions with the same RC value form a column. 114 let ColFields = ["RC"]; 115 // The key column are the non-record-form instructions. 116 let KeyCol = ["0"]; 117 // Value columns RC=1 118 let ValueCols = [["1"]]; 119 } 120 121 def getNonRecordFormOpcode : InstrMapping { 122 let FilterClass = "RecFormRel"; 123 // Instructions with the same BaseName and Interpretation64Bit values 124 // form a row. 125 let RowFields = ["BaseName", "Interpretation64Bit"]; 126 // Instructions with the same RC value form a column. 127 let ColFields = ["RC"]; 128 // The key column are the record-form instructions. 129 let KeyCol = ["1"]; 130 // Value columns are RC=0 131 let ValueCols = [["0"]]; 132 } 133 134 //===----------------------------------------------------------------------===// 135 // Register File Description 136 //===----------------------------------------------------------------------===// 137 138 include "PPCRegisterInfo.td" 139 include "PPCSchedule.td" 140 include "PPCInstrInfo.td" 141 142 //===----------------------------------------------------------------------===// 143 // PowerPC processors supported. 144 // 145 146 def : Processor<"generic", G3Itineraries, [Directive32]>; 147 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL, 148 FeatureFRES, FeatureFRSQRTE, 149 FeatureBookE]>; 150 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL, 151 FeatureFRES, FeatureFRSQRTE, 152 FeatureBookE]>; 153 def : Processor<"601", G3Itineraries, [Directive601]>; 154 def : Processor<"602", G3Itineraries, [Directive602]>; 155 def : Processor<"603", G3Itineraries, [Directive603, 156 FeatureFRES, FeatureFRSQRTE]>; 157 def : Processor<"603e", G3Itineraries, [Directive603, 158 FeatureFRES, FeatureFRSQRTE]>; 159 def : Processor<"603ev", G3Itineraries, [Directive603, 160 FeatureFRES, FeatureFRSQRTE]>; 161 def : Processor<"604", G3Itineraries, [Directive604, 162 FeatureFRES, FeatureFRSQRTE]>; 163 def : Processor<"604e", G3Itineraries, [Directive604, 164 FeatureFRES, FeatureFRSQRTE]>; 165 def : Processor<"620", G3Itineraries, [Directive620, 166 FeatureFRES, FeatureFRSQRTE]>; 167 def : Processor<"750", G4Itineraries, [Directive750, 168 FeatureFRES, FeatureFRSQRTE]>; 169 def : Processor<"g3", G3Itineraries, [Directive750, 170 FeatureFRES, FeatureFRSQRTE]>; 171 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 172 FeatureFRES, FeatureFRSQRTE]>; 173 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 174 FeatureFRES, FeatureFRSQRTE]>; 175 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 176 FeatureFRES, FeatureFRSQRTE]>; 177 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 178 FeatureFRES, FeatureFRSQRTE]>; 179 def : ProcessorModel<"970", G5Model, 180 [Directive970, FeatureAltivec, 181 FeatureMFOCRF, FeatureFSqrt, 182 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 183 Feature64Bit /*, Feature64BitRegs */]>; 184 def : ProcessorModel<"g5", G5Model, 185 [Directive970, FeatureAltivec, 186 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 187 FeatureFRES, FeatureFRSQRTE, 188 Feature64Bit /*, Feature64BitRegs */]>; 189 def : ProcessorModel<"e500mc", PPCE500mcModel, 190 [DirectiveE500mc, FeatureMFOCRF, 191 FeatureSTFIWX, FeatureBookE, FeatureISEL]>; 192 def : ProcessorModel<"e5500", PPCE5500Model, 193 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 194 FeatureSTFIWX, FeatureBookE, FeatureISEL]>; 195 def : ProcessorModel<"a2", PPCA2Model, 196 [DirectiveA2, FeatureBookE, FeatureMFOCRF, 197 FeatureFSqrt, FeatureFRE, FeatureFRES, 198 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 199 FeatureSTFIWX, FeatureLFIWAX, 200 FeatureFPRND, FeatureFPCVT, FeatureISEL, 201 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit 202 /*, Feature64BitRegs */]>; 203 def : ProcessorModel<"a2q", PPCA2Model, 204 [DirectiveA2, FeatureBookE, FeatureMFOCRF, 205 FeatureFSqrt, FeatureFRE, FeatureFRES, 206 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 207 FeatureSTFIWX, FeatureLFIWAX, 208 FeatureFPRND, FeatureFPCVT, FeatureISEL, 209 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit 210 /*, Feature64BitRegs */, FeatureQPX]>; 211 def : ProcessorModel<"pwr3", G5Model, 212 [DirectivePwr3, FeatureAltivec, 213 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 214 FeatureSTFIWX, Feature64Bit]>; 215 def : ProcessorModel<"pwr4", G5Model, 216 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 217 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 218 FeatureSTFIWX, Feature64Bit]>; 219 def : ProcessorModel<"pwr5", G5Model, 220 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 221 FeatureFSqrt, FeatureFRE, FeatureFRES, 222 FeatureFRSQRTE, FeatureFRSQRTES, 223 FeatureSTFIWX, Feature64Bit]>; 224 def : ProcessorModel<"pwr5x", G5Model, 225 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 226 FeatureFSqrt, FeatureFRE, FeatureFRES, 227 FeatureFRSQRTE, FeatureFRSQRTES, 228 FeatureSTFIWX, FeatureFPRND, Feature64Bit]>; 229 def : ProcessorModel<"pwr6", G5Model, 230 [DirectivePwr6, FeatureAltivec, 231 FeatureMFOCRF, FeatureFSqrt, FeatureFRE, 232 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 233 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 234 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */]>; 235 def : ProcessorModel<"pwr6x", G5Model, 236 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 237 FeatureFSqrt, FeatureFRE, FeatureFRES, 238 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 239 FeatureSTFIWX, FeatureLFIWAX, 240 FeatureFPRND, Feature64Bit]>; 241 def : ProcessorModel<"pwr7", G5Model, 242 [DirectivePwr7, FeatureAltivec, 243 FeatureMFOCRF, FeatureFSqrt, FeatureFRE, 244 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 245 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, 246 FeatureFPRND, FeatureFPCVT, FeatureISEL, 247 FeaturePOPCNTD, FeatureLDBRX, 248 Feature64Bit /*, Feature64BitRegs */]>; 249 def : Processor<"ppc", G3Itineraries, [Directive32]>; 250 def : ProcessorModel<"ppc64", G5Model, 251 [Directive64, FeatureAltivec, 252 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 253 FeatureFRSQRTE, FeatureSTFIWX, 254 Feature64Bit /*, Feature64BitRegs */]>; 255 def : ProcessorModel<"ppc64le", G5Model, 256 [Directive64, FeatureAltivec, 257 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 258 FeatureFRSQRTE, FeatureSTFIWX, 259 Feature64Bit /*, Feature64BitRegs */]>; 260 261 //===----------------------------------------------------------------------===// 262 // Calling Conventions 263 //===----------------------------------------------------------------------===// 264 265 include "PPCCallingConv.td" 266 267 def PPCInstrInfo : InstrInfo { 268 let isLittleEndianEncoding = 1; 269 } 270 271 def PPCAsmWriter : AsmWriter { 272 string AsmWriterClassName = "InstPrinter"; 273 bit isMCAsmWriter = 1; 274 } 275 276 def PPCAsmParser : AsmParser { 277 let ShouldEmitMatchRegisterName = 0; 278 } 279 280 def PPCAsmParserVariant : AsmParserVariant { 281 int Variant = 0; 282 283 // We do not use hard coded registers in asm strings. However, some 284 // InstAlias definitions use immediate literals. Set RegisterPrefix 285 // so that those are not misinterpreted as registers. 286 string RegisterPrefix = "%"; 287 } 288 289 def PPC : Target { 290 // Information about the instructions. 291 let InstructionSet = PPCInstrInfo; 292 293 let AssemblyWriters = [PPCAsmWriter]; 294 let AssemblyParsers = [PPCAsmParser]; 295 let AssemblyParserVariants = [PPCAsmParserVariant]; 296 } 297
