1 //===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This describes the calling conventions for the PowerPC 32- and 64-bit 11 // architectures. 12 // 13 //===----------------------------------------------------------------------===// 14 15 /// CCIfSubtarget - Match if the current subtarget has a feature F. 16 class CCIfSubtarget<string F, CCAction A> 17 : CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>; 18 19 //===----------------------------------------------------------------------===// 20 // Return Value Calling Convention 21 //===----------------------------------------------------------------------===// 22 23 // Return-value convention for PowerPC 24 def RetCC_PPC : CallingConv<[ 25 // On PPC64, integer return values are always promoted to i64 26 CCIfType<[i32], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>, 27 28 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, 29 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>, 30 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, 31 32 CCIfType<[f32], CCAssignToReg<[F1, F2]>>, 33 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>, 34 35 // Vector types are always returned in V2. 36 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>> 37 ]>; 38 39 40 //===----------------------------------------------------------------------===// 41 // PowerPC System V Release 4 32-bit ABI 42 //===----------------------------------------------------------------------===// 43 44 def CC_PPC32_SVR4_Common : CallingConv<[ 45 // The ABI requires i64 to be passed in two adjacent registers with the first 46 // register having an odd register number. 47 CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>, 48 49 // The first 8 integer arguments are passed in integer registers. 50 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, 51 52 // Make sure the i64 words from a long double are either both passed in 53 // registers or both passed on the stack. 54 CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>, 55 56 // FP values are passed in F1 - F8. 57 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, 58 59 // Split arguments have an alignment of 8 bytes on the stack. 60 CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>, 61 62 CCIfType<[i32], CCAssignToStack<4, 4>>, 63 64 // Floats are stored in double precision format, thus they have the same 65 // alignment and size as doubles. 66 CCIfType<[f32,f64], CCAssignToStack<8, 8>>, 67 68 // Vectors get 16-byte stack slots that are 16-byte aligned. 69 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>> 70 ]>; 71 72 // This calling convention puts vector arguments always on the stack. It is used 73 // to assign vector arguments which belong to the variable portion of the 74 // parameter list of a variable argument function. 75 def CC_PPC32_SVR4_VarArg : CallingConv<[ 76 CCDelegateTo<CC_PPC32_SVR4_Common> 77 ]>; 78 79 // In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to 80 // put vector arguments in vector registers before putting them on the stack. 81 def CC_PPC32_SVR4 : CallingConv<[ 82 // The first 12 Vector arguments are passed in AltiVec registers. 83 CCIfType<[v16i8, v8i16, v4i32, v4f32], 84 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>, 85 86 CCDelegateTo<CC_PPC32_SVR4_Common> 87 ]>; 88 89 // Helper "calling convention" to handle aggregate by value arguments. 90 // Aggregate by value arguments are always placed in the local variable space 91 // of the caller. This calling convention is only used to assign those stack 92 // offsets in the callers stack frame. 93 // 94 // Still, the address of the aggregate copy in the callers stack frame is passed 95 // in a GPR (or in the parameter list area if all GPRs are allocated) from the 96 // caller to the callee. The location for the address argument is assigned by 97 // the CC_PPC32_SVR4 calling convention. 98 // 99 // The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are 100 // not passed by value. 101 102 def CC_PPC32_SVR4_ByVal : CallingConv<[ 103 CCIfByVal<CCPassByVal<4, 4>>, 104 105 CCCustom<"CC_PPC32_SVR4_Custom_Dummy"> 106 ]>; 107 108 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27, 109 V28, V29, V30, V31)>; 110 111 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20, 112 R21, R22, R23, R24, R25, R26, R27, R28, 113 R29, R30, R31, F14, F15, F16, F17, F18, 114 F19, F20, F21, F22, F23, F24, F25, F26, 115 F27, F28, F29, F30, F31, CR2, CR3, CR4 116 )>; 117 118 def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>; 119 120 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, 121 R21, R22, R23, R24, R25, R26, R27, R28, 122 R29, R30, R31, F14, F15, F16, F17, F18, 123 F19, F20, F21, F22, F23, F24, F25, F26, 124 F27, F28, F29, F30, F31, CR2, CR3, CR4 125 )>; 126 127 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>; 128 129 def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20, 130 X21, X22, X23, X24, X25, X26, X27, X28, 131 X29, X30, X31, F14, F15, F16, F17, F18, 132 F19, F20, F21, F22, F23, F24, F25, F26, 133 F27, F28, F29, F30, F31, CR2, CR3, CR4 134 )>; 135 136 def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>; 137 138 def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, 139 X21, X22, X23, X24, X25, X26, X27, X28, 140 X29, X30, X31, F14, F15, F16, F17, F18, 141 F19, F20, F21, F22, F23, F24, F25, F26, 142 F27, F28, F29, F30, F31, CR2, CR3, CR4 143 )>; 144 145 146 def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>; 147 148 def CSR_NoRegs : CalleeSavedRegs<(add)>; 149 150
