1 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Altivec extension to the PowerPC instruction set. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Altivec transformation functions and pattern fragments. 16 // 17 18 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 19 // of that type. 20 def vnot_ppc : PatFrag<(ops node:$in), 21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 22 23 def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 24 (vector_shuffle node:$lhs, node:$rhs), [{ 25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 26 }]>; 27 def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 28 (vector_shuffle node:$lhs, node:$rhs), [{ 29 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 30 }]>; 31 def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 32 (vector_shuffle node:$lhs, node:$rhs), [{ 33 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 34 }]>; 35 def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 36 (vector_shuffle node:$lhs, node:$rhs), [{ 37 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 38 }]>; 39 40 41 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 42 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 43 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 44 }]>; 45 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 47 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 48 }]>; 49 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 51 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 52 }]>; 53 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 55 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 56 }]>; 57 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 59 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 60 }]>; 61 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 62 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 63 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 64 }]>; 65 66 67 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 69 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 70 }]>; 71 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 72 (vector_shuffle node:$lhs, node:$rhs), [{ 73 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 74 }]>; 75 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 76 (vector_shuffle node:$lhs, node:$rhs), [{ 77 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 78 }]>; 79 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 80 (vector_shuffle node:$lhs, node:$rhs), [{ 81 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 82 }]>; 83 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 84 (vector_shuffle node:$lhs, node:$rhs), [{ 85 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 86 }]>; 87 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 88 (vector_shuffle node:$lhs, node:$rhs), [{ 89 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 90 }]>; 91 92 93 def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 94 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false)); 95 }]>; 96 def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 97 (vector_shuffle node:$lhs, node:$rhs), [{ 98 return PPC::isVSLDOIShuffleMask(N, false) != -1; 99 }], VSLDOI_get_imm>; 100 101 102 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 103 /// vector_shuffle(X,undef,mask) by the dag combiner. 104 def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 105 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true)); 106 }]>; 107 def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 108 (vector_shuffle node:$lhs, node:$rhs), [{ 109 return PPC::isVSLDOIShuffleMask(N, true) != -1; 110 }], VSLDOI_unary_get_imm>; 111 112 113 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 114 def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 115 return getI32Imm(PPC::getVSPLTImmediate(N, 1)); 116 }]>; 117 def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 118 (vector_shuffle node:$lhs, node:$rhs), [{ 119 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 120 }], VSPLTB_get_imm>; 121 def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 122 return getI32Imm(PPC::getVSPLTImmediate(N, 2)); 123 }]>; 124 def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 125 (vector_shuffle node:$lhs, node:$rhs), [{ 126 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 127 }], VSPLTH_get_imm>; 128 def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 129 return getI32Imm(PPC::getVSPLTImmediate(N, 4)); 130 }]>; 131 def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 132 (vector_shuffle node:$lhs, node:$rhs), [{ 133 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 134 }], VSPLTW_get_imm>; 135 136 137 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 138 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 139 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 140 }]>; 141 def vecspltisb : PatLeaf<(build_vector), [{ 142 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 143 }], VSPLTISB_get_imm>; 144 145 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 146 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 147 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 148 }]>; 149 def vecspltish : PatLeaf<(build_vector), [{ 150 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 151 }], VSPLTISH_get_imm>; 152 153 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 154 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 155 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 156 }]>; 157 def vecspltisw : PatLeaf<(build_vector), [{ 158 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 159 }], VSPLTISW_get_imm>; 160 161 //===----------------------------------------------------------------------===// 162 // Helpers for defining instructions that directly correspond to intrinsics. 163 164 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 165 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 166 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 167 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 168 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 169 170 // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 171 // inputs doesn't match the type of the output. 172 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 173 ValueType InTy> 174 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 175 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 176 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 177 178 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 179 // input types and an output type. 180 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 181 ValueType In1Ty, ValueType In2Ty> 182 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 183 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 184 [(set OutTy:$vD, 185 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 186 187 // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 188 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 189 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 190 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 191 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 192 193 // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 194 // inputs doesn't match the type of the output. 195 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 196 ValueType InTy> 197 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 198 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 199 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 200 201 // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 202 // input types and an output type. 203 class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 204 ValueType In1Ty, ValueType In2Ty> 205 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 206 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 207 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 208 209 // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 210 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 211 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 212 !strconcat(opc, " $vD, $vB"), VecFP, 213 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 214 215 // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 216 // inputs doesn't match the type of the output. 217 class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 218 ValueType InTy> 219 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 220 !strconcat(opc, " $vD, $vB"), VecFP, 221 [(set OutTy:$vD, (IntID InTy:$vB))]>; 222 223 //===----------------------------------------------------------------------===// 224 // Instruction Definitions. 225 226 def HasAltivec : Predicate<"PPCSubTarget.hasAltivec()">; 227 let Predicates = [HasAltivec] in { 228 229 let isCodeGenOnly = 1 in { 230 def DSS : DSS_Form<822, (outs), 231 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), 232 "dss $STRM", LdStLoad /*FIXME*/, []>; 233 def DSSALL : DSS_Form<822, (outs), 234 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), 235 "dssall", LdStLoad /*FIXME*/, []>; 236 def DST : DSS_Form<342, (outs), 237 (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), 238 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 239 def DSTT : DSS_Form<342, (outs), 240 (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), 241 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 242 def DSTST : DSS_Form<374, (outs), 243 (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), 244 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 245 def DSTSTT : DSS_Form<374, (outs), 246 (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), 247 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 248 249 def DST64 : DSS_Form<342, (outs), 250 (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), 251 "dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 252 def DSTT64 : DSS_Form<342, (outs), 253 (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), 254 "dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 255 def DSTST64 : DSS_Form<374, (outs), 256 (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), 257 "dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 258 def DSTSTT64 : DSS_Form<374, (outs), 259 (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), 260 "dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>; 261 } 262 263 def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), 264 "mfvscr $vD", LdStStore, 265 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 266 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), 267 "mtvscr $vB", LdStLoad, 268 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 269 270 let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. 271 def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src), 272 "lvebx $vD, $src", LdStLoad, 273 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 274 def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src), 275 "lvehx $vD, $src", LdStLoad, 276 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 277 def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src), 278 "lvewx $vD, $src", LdStLoad, 279 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 280 def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src), 281 "lvx $vD, $src", LdStLoad, 282 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 283 def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src), 284 "lvxl $vD, $src", LdStLoad, 285 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 286 } 287 288 def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src), 289 "lvsl $vD, $src", LdStLoad, 290 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 291 PPC970_Unit_LSU; 292 def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src), 293 "lvsr $vD, $src", LdStLoad, 294 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 295 PPC970_Unit_LSU; 296 297 let PPC970_Unit = 2 in { // Stores. 298 def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), 299 "stvebx $rS, $dst", LdStStore, 300 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 301 def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), 302 "stvehx $rS, $dst", LdStStore, 303 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 304 def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), 305 "stvewx $rS, $dst", LdStStore, 306 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 307 def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), 308 "stvx $rS, $dst", LdStStore, 309 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 310 def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), 311 "stvxl $rS, $dst", LdStStore, 312 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 313 } 314 315 let PPC970_Unit = 5 in { // VALU Operations. 316 // VA-Form instructions. 3-input AltiVec ops. 317 def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 318 "vmaddfp $vD, $vA, $vC, $vB", VecFP, 319 [(set v4f32:$vD, 320 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 321 322 // FIXME: The fma+fneg pattern won't match because fneg is not legal. 323 def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 324 "vnmsubfp $vD, $vA, $vC, $vB", VecFP, 325 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 326 (fneg v4f32:$vB))))]>; 327 328 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 329 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 330 v8i16>; 331 def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 332 333 def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 334 v4i32, v4i32, v16i8>; 335 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 336 337 // Shuffles. 338 def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH), 339 "vsldoi $vD, $vA, $vB, $SH", VecFP, 340 [(set v16i8:$vD, 341 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>; 342 343 // VX-Form instructions. AltiVec arithmetic ops. 344 def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 345 "vaddfp $vD, $vA, $vB", VecFP, 346 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 347 348 def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 349 "vaddubm $vD, $vA, $vB", VecGeneral, 350 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 351 def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 352 "vadduhm $vD, $vA, $vB", VecGeneral, 353 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 354 def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 355 "vadduwm $vD, $vA, $vB", VecGeneral, 356 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 357 358 def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 359 def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 360 def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 361 def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 362 def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 363 def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 364 def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 365 366 367 def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 368 "vand $vD, $vA, $vB", VecFP, 369 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 370 def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 371 "vandc $vD, $vA, $vB", VecFP, 372 [(set v4i32:$vD, (and v4i32:$vA, 373 (vnot_ppc v4i32:$vB)))]>; 374 375 def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 376 "vcfsx $vD, $vB, $UIMM", VecFP, 377 [(set v4f32:$vD, 378 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>; 379 def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 380 "vcfux $vD, $vB, $UIMM", VecFP, 381 [(set v4f32:$vD, 382 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>; 383 def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 384 "vctsxs $vD, $vB, $UIMM", VecFP, 385 [(set v4i32:$vD, 386 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>; 387 def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 388 "vctuxs $vD, $vB, $UIMM", VecFP, 389 [(set v4i32:$vD, 390 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>; 391 392 // Defines with the UIM field set to 0 for floating-point 393 // to integer (fp_to_sint/fp_to_uint) conversions and integer 394 // to floating-point (sint_to_fp/uint_to_fp) conversions. 395 let isCodeGenOnly = 1, VA = 0 in { 396 def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), 397 "vcfsx $vD, $vB, 0", VecFP, 398 [(set v4f32:$vD, 399 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 400 def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), 401 "vctuxs $vD, $vB, 0", VecFP, 402 [(set v4i32:$vD, 403 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 404 def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), 405 "vcfux $vD, $vB, 0", VecFP, 406 [(set v4f32:$vD, 407 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 408 def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), 409 "vctsxs $vD, $vB, 0", VecFP, 410 [(set v4i32:$vD, 411 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 412 } 413 def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 414 def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 415 416 def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 417 def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 418 def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 419 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 420 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 421 def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 422 423 def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 424 def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 425 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 426 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 427 def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 428 def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 429 def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 430 def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 431 def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 432 def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 433 def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 434 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 435 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 436 def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 437 438 def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 439 "vmrghb $vD, $vA, $vB", VecFP, 440 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 441 def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 442 "vmrghh $vD, $vA, $vB", VecFP, 443 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 444 def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 445 "vmrghw $vD, $vA, $vB", VecFP, 446 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 447 def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 448 "vmrglb $vD, $vA, $vB", VecFP, 449 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 450 def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 451 "vmrglh $vD, $vA, $vB", VecFP, 452 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 453 def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 454 "vmrglw $vD, $vA, $vB", VecFP, 455 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 456 457 def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 458 v4i32, v16i8, v4i32>; 459 def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 460 v4i32, v8i16, v4i32>; 461 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 462 v4i32, v8i16, v4i32>; 463 def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 464 v4i32, v16i8, v4i32>; 465 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 466 v4i32, v8i16, v4i32>; 467 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 468 v4i32, v8i16, v4i32>; 469 470 def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 471 v8i16, v16i8>; 472 def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 473 v4i32, v8i16>; 474 def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 475 v8i16, v16i8>; 476 def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 477 v4i32, v8i16>; 478 def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 479 v8i16, v16i8>; 480 def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 481 v4i32, v8i16>; 482 def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 483 v8i16, v16i8>; 484 def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 485 v4i32, v8i16>; 486 487 def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 488 def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 489 def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 490 def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 491 def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 492 def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 493 494 def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 495 496 def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 497 "vsubfp $vD, $vA, $vB", VecGeneral, 498 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 499 def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 500 "vsububm $vD, $vA, $vB", VecGeneral, 501 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 502 def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 503 "vsubuhm $vD, $vA, $vB", VecGeneral, 504 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 505 def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 506 "vsubuwm $vD, $vA, $vB", VecGeneral, 507 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 508 509 def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 510 def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 511 def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 512 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 513 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 514 def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 515 516 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 517 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 518 519 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, 520 v4i32, v16i8, v4i32>; 521 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 522 v4i32, v8i16, v4i32>; 523 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 524 v4i32, v16i8, v4i32>; 525 526 def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 527 "vnor $vD, $vA, $vB", VecFP, 528 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, 529 v4i32:$vB)))]>; 530 def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 531 "vor $vD, $vA, $vB", VecFP, 532 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 533 def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 534 "vxor $vD, $vA, $vB", VecFP, 535 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 536 537 def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 538 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 539 def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 540 541 def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 542 def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 543 544 def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 545 def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 546 def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 547 548 def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 549 "vspltb $vD, $vB, $UIMM", VecPerm, 550 [(set v16i8:$vD, 551 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 552 def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 553 "vsplth $vD, $vB, $UIMM", VecPerm, 554 [(set v16i8:$vD, 555 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 556 def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 557 "vspltw $vD, $vB, $UIMM", VecPerm, 558 [(set v16i8:$vD, 559 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 560 561 def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 562 def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 563 564 def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 565 def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 566 def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 567 def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 568 def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 569 def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 570 571 572 def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), 573 "vspltisb $vD, $SIMM", VecPerm, 574 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 575 def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), 576 "vspltish $vD, $SIMM", VecPerm, 577 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 578 def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), 579 "vspltisw $vD, $SIMM", VecPerm, 580 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 581 582 // Vector Pack. 583 def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 584 v8i16, v4i32>; 585 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 586 v16i8, v8i16>; 587 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 588 v16i8, v8i16>; 589 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 590 v16i8, v4i32>; 591 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 592 v8i16, v4i32>; 593 def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 594 "vpkuhum $vD, $vA, $vB", VecFP, 595 [(set v16i8:$vD, 596 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 597 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 598 v16i8, v8i16>; 599 def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 600 "vpkuwum $vD, $vA, $vB", VecFP, 601 [(set v16i8:$vD, 602 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 603 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 604 v8i16, v4i32>; 605 606 // Vector Unpack. 607 def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 608 v4i32, v8i16>; 609 def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 610 v8i16, v16i8>; 611 def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 612 v4i32, v8i16>; 613 def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 614 v4i32, v8i16>; 615 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 616 v8i16, v16i8>; 617 def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 618 v4i32, v8i16>; 619 620 621 // Altivec Comparisons. 622 623 class VCMP<bits<10> xo, string asmstr, ValueType Ty> 624 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),asmstr,VecFPCompare, 625 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 626 class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 627 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),asmstr,VecFPCompare, 628 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { 629 let Defs = [CR6]; 630 let RC = 1; 631 } 632 633 // f32 element comparisons.0 634 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 635 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 636 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 637 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 638 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 639 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 640 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 641 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 642 643 // i8 element comparisons. 644 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 645 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 646 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 647 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 648 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 649 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 650 651 // i16 element comparisons. 652 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 653 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 654 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 655 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 656 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 657 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 658 659 // i32 element comparisons. 660 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 661 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 662 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 663 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 664 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 665 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 666 667 let isCodeGenOnly = 1 in { 668 def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 669 "vxor $vD, $vD, $vD", VecFP, 670 [(set v16i8:$vD, (v16i8 immAllZerosV))]>; 671 def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 672 "vxor $vD, $vD, $vD", VecFP, 673 [(set v8i16:$vD, (v8i16 immAllZerosV))]>; 674 def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 675 "vxor $vD, $vD, $vD", VecFP, 676 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 677 678 let IMM=-1 in { 679 def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), 680 "vspltisw $vD, -1", VecFP, 681 [(set v16i8:$vD, (v16i8 immAllOnesV))]>; 682 def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), 683 "vspltisw $vD, -1", VecFP, 684 [(set v8i16:$vD, (v8i16 immAllOnesV))]>; 685 def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), 686 "vspltisw $vD, -1", VecFP, 687 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 688 } 689 } 690 } // VALU Operations. 691 692 //===----------------------------------------------------------------------===// 693 // Additional Altivec Patterns 694 // 695 696 // DS* intrinsics 697 def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; 698 def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; 699 700 // * 32-bit 701 def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM), 702 (DST 0, imm:$STRM, $rA, $rB)>; 703 def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM), 704 (DSTT 1, imm:$STRM, $rA, $rB)>; 705 def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM), 706 (DSTST 0, imm:$STRM, $rA, $rB)>; 707 def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM), 708 (DSTSTT 1, imm:$STRM, $rA, $rB)>; 709 710 // * 64-bit 711 def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM), 712 (DST64 0, imm:$STRM, $rA, $rB)>; 713 def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM), 714 (DSTT64 1, imm:$STRM, $rA, $rB)>; 715 def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM), 716 (DSTST64 0, imm:$STRM, $rA, $rB)>; 717 def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM), 718 (DSTSTT64 1, imm:$STRM, $rA, $rB)>; 719 720 // Loads. 721 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 722 723 // Stores. 724 def : Pat<(store v4i32:$rS, xoaddr:$dst), 725 (STVX $rS, xoaddr:$dst)>; 726 727 // Bit conversions. 728 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 729 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 730 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 731 732 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 733 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 734 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 735 736 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 737 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 738 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 739 740 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 741 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 742 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 743 744 // Shuffles. 745 746 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 747 def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 748 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 749 def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 750 (VPKUWUM $vA, $vA)>; 751 def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 752 (VPKUHUM $vA, $vA)>; 753 754 // Match vmrg*(x,x) 755 def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 756 (VMRGLB $vA, $vA)>; 757 def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 758 (VMRGLH $vA, $vA)>; 759 def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 760 (VMRGLW $vA, $vA)>; 761 def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 762 (VMRGHB $vA, $vA)>; 763 def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 764 (VMRGHH $vA, $vA)>; 765 def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 766 (VMRGHW $vA, $vA)>; 767 768 // Logical Operations 769 def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; 770 771 def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), 772 (VNOR $A, $B)>; 773 def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), 774 (VANDC $A, $B)>; 775 776 def : Pat<(fmul v4f32:$vA, v4f32:$vB), 777 (VMADDFP $vA, $vB, 778 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>; 779 780 // Fused multiply add and multiply sub for packed float. These are represented 781 // separately from the real instructions above, for operations that must have 782 // the additional precision, such as Newton-Rhapson (used by divide, sqrt) 783 def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 784 (VMADDFP $A, $B, $C)>; 785 def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 786 (VNMSUBFP $A, $B, $C)>; 787 788 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 789 (VMADDFP $A, $B, $C)>; 790 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 791 (VNMSUBFP $A, $B, $C)>; 792 793 def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 794 (VPERM $vA, $vB, $vC)>; 795 796 def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 797 def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 798 799 // Vector shifts 800 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 801 (v16i8 (VSLB $vA, $vB))>; 802 def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 803 (v8i16 (VSLH $vA, $vB))>; 804 def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 805 (v4i32 (VSLW $vA, $vB))>; 806 807 def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 808 (v16i8 (VSRB $vA, $vB))>; 809 def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 810 (v8i16 (VSRH $vA, $vB))>; 811 def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 812 (v4i32 (VSRW $vA, $vB))>; 813 814 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 815 (v16i8 (VSRAB $vA, $vB))>; 816 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 817 (v8i16 (VSRAH $vA, $vB))>; 818 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 819 (v4i32 (VSRAW $vA, $vB))>; 820 821 // Float to integer and integer to float conversions 822 def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 823 (VCTSXS_0 $vA)>; 824 def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 825 (VCTUXS_0 $vA)>; 826 def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 827 (VCFSX_0 $vA)>; 828 def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 829 (VCFUX_0 $vA)>; 830 831 // Floating-point rounding 832 def : Pat<(v4f32 (ffloor v4f32:$vA)), 833 (VRFIM $vA)>; 834 def : Pat<(v4f32 (fceil v4f32:$vA)), 835 (VRFIP $vA)>; 836 def : Pat<(v4f32 (ftrunc v4f32:$vA)), 837 (VRFIZ $vA)>; 838 def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 839 (VRFIN $vA)>; 840 841 } // end HasAltivec 842 843
