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      1 //==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 //===----------------------------------------------------------------------===//
     11 // Select instructions
     12 //===----------------------------------------------------------------------===//
     13 
     14 // C's ?: operator for floating-point operands.
     15 def SelectF32  : SelectWrapper<FP32>;
     16 def SelectF64  : SelectWrapper<FP64>;
     17 def SelectF128 : SelectWrapper<FP128>;
     18 
     19 defm CondStoreF32 : CondStores<FP32, nonvolatile_store,
     20                                nonvolatile_load, bdxaddr20only>;
     21 defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
     22                                nonvolatile_load, bdxaddr20only>;
     23 
     24 //===----------------------------------------------------------------------===//
     25 // Move instructions
     26 //===----------------------------------------------------------------------===//
     27 
     28 // Load zero.
     29 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
     30   def LZER : InherentRRE<"lze", 0xB374, FP32,  (fpimm0)>;
     31   def LZDR : InherentRRE<"lzd", 0xB375, FP64,  (fpimm0)>;
     32   def LZXR : InherentRRE<"lzx", 0xB376, FP128, (fpimm0)>;
     33 }
     34 
     35 // Moves between two floating-point registers.
     36 let neverHasSideEffects = 1 in {
     37   def LER : UnaryRR <"le", 0x38,   null_frag, FP32,  FP32>;
     38   def LDR : UnaryRR <"ld", 0x28,   null_frag, FP64,  FP64>;
     39   def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>;
     40 }
     41 
     42 // Moves between two floating-point registers that also set the condition
     43 // codes.
     44 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
     45   defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>;
     46   defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
     47   defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>;
     48 }
     49 def : CompareZeroFP<LTEBRCompare, FP32>;
     50 def : CompareZeroFP<LTDBRCompare, FP64>;
     51 def : CompareZeroFP<LTXBRCompare, FP128>;
     52 
     53 // Moves between 64-bit integer and floating-point registers.
     54 def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
     55 def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;
     56 
     57 // fcopysign with an FP32 result.
     58 let isCodeGenOnly = 1 in {
     59   def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>;
     60   def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>;
     61 }
     62 
     63 // The sign of an FP128 is in the high register.
     64 def : Pat<(fcopysign FP32:$src1, FP128:$src2),
     65           (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>;
     66 
     67 // fcopysign with an FP64 result.
     68 let isCodeGenOnly = 1 in
     69   def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>;
     70 def CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>;
     71 
     72 // The sign of an FP128 is in the high register.
     73 def : Pat<(fcopysign FP64:$src1, FP128:$src2),
     74           (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>;
     75 
     76 // fcopysign with an FP128 result.  Use "upper" as the high half and leave
     77 // the low half as-is.
     78 class CopySign128<RegisterOperand cls, dag upper>
     79   : Pat<(fcopysign FP128:$src1, cls:$src2),
     80         (INSERT_SUBREG FP128:$src1, upper, subreg_high)>;
     81 
     82 def : CopySign128<FP32,  (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_high),
     83                                   FP32:$src2)>;
     84 def : CopySign128<FP64,  (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high),
     85                                   FP64:$src2)>;
     86 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high),
     87                                   (EXTRACT_SUBREG FP128:$src2, subreg_high))>;
     88 
     89 defm LoadStoreF32  : MVCLoadStore<load, store, f32,  MVCWrapper, 4>;
     90 defm LoadStoreF64  : MVCLoadStore<load, store, f64,  MVCWrapper, 8>;
     91 defm LoadStoreF128 : MVCLoadStore<load, store, f128, MVCWrapper, 16>;
     92 
     93 //===----------------------------------------------------------------------===//
     94 // Load instructions
     95 //===----------------------------------------------------------------------===//
     96 
     97 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
     98   defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>;
     99   defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>;
    100 
    101   // These instructions are split after register allocation, so we don't
    102   // want a custom inserter.
    103   let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
    104     def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
    105                      [(set FP128:$dst, (load bdxaddr20only128:$src))]>;
    106   }
    107 }
    108 
    109 //===----------------------------------------------------------------------===//
    110 // Store instructions
    111 //===----------------------------------------------------------------------===//
    112 
    113 let SimpleBDXStore = 1 in {
    114   defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;
    115   defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;
    116 
    117   // These instructions are split after register allocation, so we don't
    118   // want a custom inserter.
    119   let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
    120     def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
    121                      [(store FP128:$src, bdxaddr20only128:$dst)]>;
    122   }
    123 }
    124 
    125 //===----------------------------------------------------------------------===//
    126 // Conversion instructions
    127 //===----------------------------------------------------------------------===//
    128 
    129 // Convert floating-point values to narrower representations, rounding
    130 // according to the current mode.  The destination of LEXBR and LDXBR
    131 // is a 128-bit value, but only the first register of the pair is used.
    132 def LEDBR : UnaryRRE<"ledb", 0xB344, fround,    FP32,  FP64>;
    133 def LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>;
    134 def LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>;
    135 
    136 def : Pat<(f32 (fround FP128:$src)),
    137           (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_32bit)>;
    138 def : Pat<(f64 (fround FP128:$src)),
    139           (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_high)>;
    140 
    141 // Extend register floating-point values to wider representations.
    142 def LDEBR : UnaryRRE<"ldeb", 0xB304, fextend, FP64,  FP32>;
    143 def LXEBR : UnaryRRE<"lxeb", 0xB306, fextend, FP128, FP32>;
    144 def LXDBR : UnaryRRE<"lxdb", 0xB305, fextend, FP128, FP64>;
    145 
    146 // Extend memory floating-point values to wider representations.
    147 def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64,  4>;
    148 def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>;
    149 def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>;
    150 
    151 // Convert a signed integer register value to a floating-point one.
    152 def CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32,  GR32>;
    153 def CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64,  GR32>;
    154 def CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>;
    155 
    156 def CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32,  GR64>;
    157 def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64,  GR64>;
    158 def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>;
    159 
    160 // Convert a floating-point register value to a signed integer value,
    161 // with the second operand (modifier M3) specifying the rounding mode.
    162 let Defs = [CC] in {
    163   def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>;
    164   def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>;
    165   def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>;
    166 
    167   def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>;
    168   def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>;
    169   def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>;
    170 }
    171 
    172 // fp_to_sint always rounds towards zero, which is modifier value 5.
    173 def : Pat<(i32 (fp_to_sint FP32:$src)),  (CFEBR 5, FP32:$src)>;
    174 def : Pat<(i32 (fp_to_sint FP64:$src)),  (CFDBR 5, FP64:$src)>;
    175 def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>;
    176 
    177 def : Pat<(i64 (fp_to_sint FP32:$src)),  (CGEBR 5, FP32:$src)>;
    178 def : Pat<(i64 (fp_to_sint FP64:$src)),  (CGDBR 5, FP64:$src)>;
    179 def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
    180 
    181 //===----------------------------------------------------------------------===//
    182 // Unary arithmetic
    183 //===----------------------------------------------------------------------===//
    184 
    185 // Negation (Load Complement).
    186 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
    187   def LCEBR : UnaryRRE<"lceb", 0xB303, fneg, FP32,  FP32>;
    188   def LCDBR : UnaryRRE<"lcdb", 0xB313, fneg, FP64,  FP64>;
    189   def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>;
    190 }
    191 
    192 // Absolute value (Load Positive).
    193 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
    194   def LPEBR : UnaryRRE<"lpeb", 0xB300, fabs, FP32,  FP32>;
    195   def LPDBR : UnaryRRE<"lpdb", 0xB310, fabs, FP64,  FP64>;
    196   def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>;
    197 }
    198 
    199 // Negative absolute value (Load Negative).
    200 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
    201   def LNEBR : UnaryRRE<"lneb", 0xB301, fnabs, FP32,  FP32>;
    202   def LNDBR : UnaryRRE<"lndb", 0xB311, fnabs, FP64,  FP64>;
    203   def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>;
    204 }
    205 
    206 // Square root.
    207 def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32,  FP32>;
    208 def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64,  FP64>;
    209 def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>;
    210 
    211 def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>;
    212 def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>;
    213 
    214 // Round to an integer, with the second operand (modifier M3) specifying
    215 // the rounding mode.
    216 //
    217 // These forms always check for inexact conditions.  z196 added versions
    218 // that allow this to suppressed (as for fnearbyint), but we don't yet
    219 // support -march=z196.
    220 def FIEBR : UnaryRRF<"fieb", 0xB357, FP32,  FP32>;
    221 def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64,  FP64>;
    222 def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>;
    223 
    224 // frint rounds according to the current mode (modifier 0) and detects
    225 // inexact conditions.
    226 def : Pat<(frint FP32:$src),  (FIEBR 0, FP32:$src)>;
    227 def : Pat<(frint FP64:$src),  (FIDBR 0, FP64:$src)>;
    228 def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
    229 
    230 //===----------------------------------------------------------------------===//
    231 // Binary arithmetic
    232 //===----------------------------------------------------------------------===//
    233 
    234 // Addition.
    235 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
    236   let isCommutable = 1 in {
    237     def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32,  FP32>;
    238     def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64,  FP64>;
    239     def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>;
    240   }
    241   def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>;
    242   def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>;
    243 }
    244 
    245 // Subtraction.
    246 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
    247   def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32,  FP32>;
    248   def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64,  FP64>;
    249   def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>;
    250 
    251   def SEB : BinaryRXE<"seb",  0xED0B, fsub, FP32, load, 4>;
    252   def SDB : BinaryRXE<"sdb",  0xED1B, fsub, FP64, load, 8>;
    253 }
    254 
    255 // Multiplication.
    256 let isCommutable = 1 in {
    257   def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32,  FP32>;
    258   def MDBR  : BinaryRRE<"mdb",  0xB31C, fmul, FP64,  FP64>;
    259   def MXBR  : BinaryRRE<"mxb",  0xB34C, fmul, FP128, FP128>;
    260 }
    261 def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>;
    262 def MDB  : BinaryRXE<"mdb",  0xED1C, fmul, FP64, load, 8>;
    263 
    264 // f64 multiplication of two FP32 registers.
    265 def MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>;
    266 def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))),
    267           (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
    268                                 FP32:$src1, subreg_32bit), FP32:$src2)>;
    269 
    270 // f64 multiplication of an FP32 register and an f32 memory.
    271 def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>;
    272 def : Pat<(fmul (f64 (fextend FP32:$src1)),
    273                 (f64 (extloadf32 bdxaddr12only:$addr))),
    274           (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_32bit),
    275                 bdxaddr12only:$addr)>;
    276 
    277 // f128 multiplication of two FP64 registers.
    278 def MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>;
    279 def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
    280           (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
    281                                 FP64:$src1, subreg_high), FP64:$src2)>;
    282 
    283 // f128 multiplication of an FP64 register and an f64 memory.
    284 def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>;
    285 def : Pat<(fmul (f128 (fextend FP64:$src1)),
    286                 (f128 (extloadf64 bdxaddr12only:$addr))),
    287           (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_high),
    288                 bdxaddr12only:$addr)>;
    289 
    290 // Fused multiply-add.
    291 def MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>;
    292 def MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>;
    293 
    294 def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>;
    295 def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>;
    296 
    297 // Fused multiply-subtract.
    298 def MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>;
    299 def MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>;
    300 
    301 def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>;
    302 def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>;
    303 
    304 // Division.
    305 def DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32,  FP32>;
    306 def DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64,  FP64>;
    307 def DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>;
    308 
    309 def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>;
    310 def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>;
    311 
    312 //===----------------------------------------------------------------------===//
    313 // Comparisons
    314 //===----------------------------------------------------------------------===//
    315 
    316 let Defs = [CC], CCValues = 0xF in {
    317   def CEBR : CompareRRE<"ceb", 0xB309, z_cmp, FP32,  FP32>;
    318   def CDBR : CompareRRE<"cdb", 0xB319, z_cmp, FP64,  FP64>;
    319   def CXBR : CompareRRE<"cxb", 0xB349, z_cmp, FP128, FP128>;
    320 
    321   def CEB : CompareRXE<"ceb", 0xED09, z_cmp, FP32, load, 4>;
    322   def CDB : CompareRXE<"cdb", 0xED19, z_cmp, FP64, load, 8>;
    323 }
    324 
    325 //===----------------------------------------------------------------------===//
    326 // Peepholes
    327 //===----------------------------------------------------------------------===//
    328 
    329 def : Pat<(f32  fpimmneg0), (LCEBR (LZER))>;
    330 def : Pat<(f64  fpimmneg0), (LCDBR (LZDR))>;
    331 def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;
    332