1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s 2 3 declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>) 4 declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) 5 declare <2 x i64> @llvm.aarch64.neon.vacgeq(<2 x double>, <2 x double>) 6 7 define <2 x i32> @facge_from_intr_v2i32(<2 x float> %A, <2 x float> %B, <2 x float> %C) { 8 ; Using registers other than v0, v1 and v2 are possible, but would be odd. 9 ; CHECK: facge_from_intr_v2i32: 10 %val = call <2 x i32> @llvm.arm.neon.vacged(<2 x float> %A, <2 x float> %B) 11 ; CHECK: facge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 12 ret <2 x i32> %val 13 } 14 define <4 x i32> @facge_from_intr_v4i32( <4 x float> %A, <4 x float> %B) { 15 ; Using registers other than v0, v1 and v2 are possible, but would be odd. 16 ; CHECK: facge_from_intr_v4i32: 17 %val = call <4 x i32> @llvm.arm.neon.vacgeq(<4 x float> %A, <4 x float> %B) 18 ; CHECK: facge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 19 ret <4 x i32> %val 20 } 21 22 define <2 x i64> @facge_from_intr_v2i64(<2 x double> %A, <2 x double> %B) { 23 ; Using registers other than v0, v1 and v2 are possible, but would be odd. 24 ; CHECK: facge_from_intr_v2i64: 25 %val = call <2 x i64> @llvm.aarch64.neon.vacgeq(<2 x double> %A, <2 x double> %B) 26 ; CHECK: facge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 27 ret <2 x i64> %val 28 } 29 30 declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) 31 declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) 32 declare <2 x i64> @llvm.aarch64.neon.vacgtq(<2 x double>, <2 x double>) 33 34 define <2 x i32> @facgt_from_intr_v2i32(<2 x float> %A, <2 x float> %B, <2 x float> %C) { 35 ; Using registers other than v0, v1 and v2 are possible, but would be odd. 36 ; CHECK: facgt_from_intr_v2i32: 37 %val = call <2 x i32> @llvm.arm.neon.vacgtd(<2 x float> %A, <2 x float> %B) 38 ; CHECK: facgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s 39 ret <2 x i32> %val 40 } 41 define <4 x i32> @facgt_from_intr_v4i32( <4 x float> %A, <4 x float> %B) { 42 ; Using registers other than v0, v1 and v2 are possible, but would be odd. 43 ; CHECK: facgt_from_intr_v4i32: 44 %val = call <4 x i32> @llvm.arm.neon.vacgtq(<4 x float> %A, <4 x float> %B) 45 ; CHECK: facgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s 46 ret <4 x i32> %val 47 } 48 49 define <2 x i64> @facgt_from_intr_v2i64(<2 x double> %A, <2 x double> %B) { 50 ; Using registers other than v0, v1 and v2 are possible, but would be odd. 51 ; CHECK: facgt_from_intr_v2i64: 52 %val = call <2 x i64> @llvm.aarch64.neon.vacgtq(<2 x double> %A, <2 x double> %B) 53 ; CHECK: facgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d 54 ret <2 x i64> %val 55 } 56 57
