1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s 2 3 declare <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8>, <8 x i8>) 4 declare <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8>, <8 x i8>) 5 6 define <8 x i8> @test_urhadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) { 7 ; CHECK: test_urhadd_v8i8: 8 %tmp1 = call <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs) 9 ; CHECK: urhadd v0.8b, v0.8b, v1.8b 10 ret <8 x i8> %tmp1 11 } 12 13 define <8 x i8> @test_srhadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) { 14 ; CHECK: test_srhadd_v8i8: 15 %tmp1 = call <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8> %lhs, <8 x i8> %rhs) 16 ; CHECK: srhadd v0.8b, v0.8b, v1.8b 17 ret <8 x i8> %tmp1 18 } 19 20 declare <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8>, <16 x i8>) 21 declare <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8>, <16 x i8>) 22 23 define <16 x i8> @test_urhadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) { 24 ; CHECK: test_urhadd_v16i8: 25 %tmp1 = call <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs) 26 ; CHECK: urhadd v0.16b, v0.16b, v1.16b 27 ret <16 x i8> %tmp1 28 } 29 30 define <16 x i8> @test_srhadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) { 31 ; CHECK: test_srhadd_v16i8: 32 %tmp1 = call <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8> %lhs, <16 x i8> %rhs) 33 ; CHECK: srhadd v0.16b, v0.16b, v1.16b 34 ret <16 x i8> %tmp1 35 } 36 37 declare <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16>, <4 x i16>) 38 declare <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16>, <4 x i16>) 39 40 define <4 x i16> @test_urhadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 41 ; CHECK: test_urhadd_v4i16: 42 %tmp1 = call <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 43 ; CHECK: urhadd v0.4h, v0.4h, v1.4h 44 ret <4 x i16> %tmp1 45 } 46 47 define <4 x i16> @test_srhadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 48 ; CHECK: test_srhadd_v4i16: 49 %tmp1 = call <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 50 ; CHECK: srhadd v0.4h, v0.4h, v1.4h 51 ret <4 x i16> %tmp1 52 } 53 54 declare <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16>, <8 x i16>) 55 declare <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16>, <8 x i16>) 56 57 define <8 x i16> @test_urhadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) { 58 ; CHECK: test_urhadd_v8i16: 59 %tmp1 = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) 60 ; CHECK: urhadd v0.8h, v0.8h, v1.8h 61 ret <8 x i16> %tmp1 62 } 63 64 define <8 x i16> @test_srhadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) { 65 ; CHECK: test_srhadd_v8i16: 66 %tmp1 = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) 67 ; CHECK: srhadd v0.8h, v0.8h, v1.8h 68 ret <8 x i16> %tmp1 69 } 70 71 declare <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32>, <2 x i32>) 72 declare <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32>, <2 x i32>) 73 74 define <2 x i32> @test_urhadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 75 ; CHECK: test_urhadd_v2i32: 76 %tmp1 = call <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 77 ; CHECK: urhadd v0.2s, v0.2s, v1.2s 78 ret <2 x i32> %tmp1 79 } 80 81 define <2 x i32> @test_srhadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 82 ; CHECK: test_srhadd_v2i32: 83 %tmp1 = call <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 84 ; CHECK: srhadd v0.2s, v0.2s, v1.2s 85 ret <2 x i32> %tmp1 86 } 87 88 declare <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32>, <4 x i32>) 89 declare <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32>, <4 x i32>) 90 91 define <4 x i32> @test_urhadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { 92 ; CHECK: test_urhadd_v4i32: 93 %tmp1 = call <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) 94 ; CHECK: urhadd v0.4s, v0.4s, v1.4s 95 ret <4 x i32> %tmp1 96 } 97 98 define <4 x i32> @test_srhadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { 99 ; CHECK: test_srhadd_v4i32: 100 %tmp1 = call <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) 101 ; CHECK: srhadd v0.4s, v0.4s, v1.4s 102 ret <4 x i32> %tmp1 103 } 104 105 106
