1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s 2 3 declare <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8>, <8 x i8>) 4 declare <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8>, <8 x i8>) 5 6 define <8 x i8> @test_uqadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) { 7 ; CHECK: test_uqadd_v8i8: 8 %tmp1 = call <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs) 9 ; CHECK: uqadd v0.8b, v0.8b, v1.8b 10 ret <8 x i8> %tmp1 11 } 12 13 define <8 x i8> @test_sqadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) { 14 ; CHECK: test_sqadd_v8i8: 15 %tmp1 = call <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8> %lhs, <8 x i8> %rhs) 16 ; CHECK: sqadd v0.8b, v0.8b, v1.8b 17 ret <8 x i8> %tmp1 18 } 19 20 declare <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8>, <16 x i8>) 21 declare <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8>, <16 x i8>) 22 23 define <16 x i8> @test_uqadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) { 24 ; CHECK: test_uqadd_v16i8: 25 %tmp1 = call <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs) 26 ; CHECK: uqadd v0.16b, v0.16b, v1.16b 27 ret <16 x i8> %tmp1 28 } 29 30 define <16 x i8> @test_sqadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) { 31 ; CHECK: test_sqadd_v16i8: 32 %tmp1 = call <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8> %lhs, <16 x i8> %rhs) 33 ; CHECK: sqadd v0.16b, v0.16b, v1.16b 34 ret <16 x i8> %tmp1 35 } 36 37 declare <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16>, <4 x i16>) 38 declare <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16>, <4 x i16>) 39 40 define <4 x i16> @test_uqadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 41 ; CHECK: test_uqadd_v4i16: 42 %tmp1 = call <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 43 ; CHECK: uqadd v0.4h, v0.4h, v1.4h 44 ret <4 x i16> %tmp1 45 } 46 47 define <4 x i16> @test_sqadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 48 ; CHECK: test_sqadd_v4i16: 49 %tmp1 = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 50 ; CHECK: sqadd v0.4h, v0.4h, v1.4h 51 ret <4 x i16> %tmp1 52 } 53 54 declare <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16>, <8 x i16>) 55 declare <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16>, <8 x i16>) 56 57 define <8 x i16> @test_uqadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) { 58 ; CHECK: test_uqadd_v8i16: 59 %tmp1 = call <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) 60 ; CHECK: uqadd v0.8h, v0.8h, v1.8h 61 ret <8 x i16> %tmp1 62 } 63 64 define <8 x i16> @test_sqadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) { 65 ; CHECK: test_sqadd_v8i16: 66 %tmp1 = call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) 67 ; CHECK: sqadd v0.8h, v0.8h, v1.8h 68 ret <8 x i16> %tmp1 69 } 70 71 declare <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32>, <2 x i32>) 72 declare <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32>, <2 x i32>) 73 74 define <2 x i32> @test_uqadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 75 ; CHECK: test_uqadd_v2i32: 76 %tmp1 = call <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 77 ; CHECK: uqadd v0.2s, v0.2s, v1.2s 78 ret <2 x i32> %tmp1 79 } 80 81 define <2 x i32> @test_sqadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 82 ; CHECK: test_sqadd_v2i32: 83 %tmp1 = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 84 ; CHECK: sqadd v0.2s, v0.2s, v1.2s 85 ret <2 x i32> %tmp1 86 } 87 88 declare <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32>, <4 x i32>) 89 declare <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32>, <4 x i32>) 90 91 define <4 x i32> @test_uqadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { 92 ; CHECK: test_uqadd_v4i32: 93 %tmp1 = call <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) 94 ; CHECK: uqadd v0.4s, v0.4s, v1.4s 95 ret <4 x i32> %tmp1 96 } 97 98 define <4 x i32> @test_sqadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { 99 ; CHECK: test_sqadd_v4i32: 100 %tmp1 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) 101 ; CHECK: sqadd v0.4s, v0.4s, v1.4s 102 ret <4 x i32> %tmp1 103 } 104 105 declare <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64>, <1 x i64>) 106 declare <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64>, <1 x i64>) 107 108 define <1 x i64> @test_uqadd_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) { 109 ; CHECK: test_uqadd_v1i64: 110 %tmp1 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs) 111 ; CHECK: uqadd d0, d0, d1 112 ret <1 x i64> %tmp1 113 } 114 115 define <1 x i64> @test_sqadd_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) { 116 ; CHECK: test_sqadd_v1i64: 117 %tmp1 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %lhs, <1 x i64> %rhs) 118 ; CHECK: sqadd d0, d0, d1 119 ret <1 x i64> %tmp1 120 } 121 122 declare <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64>, <2 x i64>) 123 declare <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64>, <2 x i64>) 124 125 define <2 x i64> @test_uqadd_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) { 126 ; CHECK: test_uqadd_v2i64: 127 %tmp1 = call <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64> %lhs, <2 x i64> %rhs) 128 ; CHECK: uqadd v0.2d, v0.2d, v1.2d 129 ret <2 x i64> %tmp1 130 } 131 132 define <2 x i64> @test_sqadd_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) { 133 ; CHECK: test_sqadd_v2i64: 134 %tmp1 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %lhs, <2 x i64> %rhs) 135 ; CHECK: sqadd v0.2d, v0.2d, v1.2d 136 ret <2 x i64> %tmp1 137 } 138 139 declare <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8>, <8 x i8>) 140 declare <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8>, <8 x i8>) 141 142 define <8 x i8> @test_uqsub_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) { 143 ; CHECK: test_uqsub_v8i8: 144 %tmp1 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs) 145 ; CHECK: uqsub v0.8b, v0.8b, v1.8b 146 ret <8 x i8> %tmp1 147 } 148 149 define <8 x i8> @test_sqsub_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) { 150 ; CHECK: test_sqsub_v8i8: 151 %tmp1 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %lhs, <8 x i8> %rhs) 152 ; CHECK: sqsub v0.8b, v0.8b, v1.8b 153 ret <8 x i8> %tmp1 154 } 155 156 declare <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8>, <16 x i8>) 157 declare <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8>, <16 x i8>) 158 159 define <16 x i8> @test_uqsub_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) { 160 ; CHECK: test_uqsub_v16i8: 161 %tmp1 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs) 162 ; CHECK: uqsub v0.16b, v0.16b, v1.16b 163 ret <16 x i8> %tmp1 164 } 165 166 define <16 x i8> @test_sqsub_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) { 167 ; CHECK: test_sqsub_v16i8: 168 %tmp1 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %lhs, <16 x i8> %rhs) 169 ; CHECK: sqsub v0.16b, v0.16b, v1.16b 170 ret <16 x i8> %tmp1 171 } 172 173 declare <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16>, <4 x i16>) 174 declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>) 175 176 define <4 x i16> @test_uqsub_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 177 ; CHECK: test_uqsub_v4i16: 178 %tmp1 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 179 ; CHECK: uqsub v0.4h, v0.4h, v1.4h 180 ret <4 x i16> %tmp1 181 } 182 183 define <4 x i16> @test_sqsub_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 184 ; CHECK: test_sqsub_v4i16: 185 %tmp1 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 186 ; CHECK: sqsub v0.4h, v0.4h, v1.4h 187 ret <4 x i16> %tmp1 188 } 189 190 declare <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16>, <8 x i16>) 191 declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>) 192 193 define <8 x i16> @test_uqsub_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) { 194 ; CHECK: test_uqsub_v8i16: 195 %tmp1 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) 196 ; CHECK: uqsub v0.8h, v0.8h, v1.8h 197 ret <8 x i16> %tmp1 198 } 199 200 define <8 x i16> @test_sqsub_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) { 201 ; CHECK: test_sqsub_v8i16: 202 %tmp1 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) 203 ; CHECK: sqsub v0.8h, v0.8h, v1.8h 204 ret <8 x i16> %tmp1 205 } 206 207 declare <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32>, <2 x i32>) 208 declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>) 209 210 define <2 x i32> @test_uqsub_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 211 ; CHECK: test_uqsub_v2i32: 212 %tmp1 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 213 ; CHECK: uqsub v0.2s, v0.2s, v1.2s 214 ret <2 x i32> %tmp1 215 } 216 217 define <2 x i32> @test_sqsub_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 218 ; CHECK: test_sqsub_v2i32: 219 %tmp1 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 220 ; CHECK: sqsub v0.2s, v0.2s, v1.2s 221 ret <2 x i32> %tmp1 222 } 223 224 declare <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32>, <4 x i32>) 225 declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>) 226 227 define <4 x i32> @test_uqsub_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { 228 ; CHECK: test_uqsub_v4i32: 229 %tmp1 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) 230 ; CHECK: uqsub v0.4s, v0.4s, v1.4s 231 ret <4 x i32> %tmp1 232 } 233 234 define <4 x i32> @test_sqsub_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { 235 ; CHECK: test_sqsub_v4i32: 236 %tmp1 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) 237 ; CHECK: sqsub v0.4s, v0.4s, v1.4s 238 ret <4 x i32> %tmp1 239 } 240 241 declare <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64>, <2 x i64>) 242 declare <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64>, <2 x i64>) 243 244 define <2 x i64> @test_uqsub_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) { 245 ; CHECK: test_uqsub_v2i64: 246 %tmp1 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %lhs, <2 x i64> %rhs) 247 ; CHECK: uqsub v0.2d, v0.2d, v1.2d 248 ret <2 x i64> %tmp1 249 } 250 251 define <2 x i64> @test_sqsub_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) { 252 ; CHECK: test_sqsub_v2i64: 253 %tmp1 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %lhs, <2 x i64> %rhs) 254 ; CHECK: sqsub v0.2d, v0.2d, v1.2d 255 ret <2 x i64> %tmp1 256 } 257 258 declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>) 259 declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>) 260 261 define <1 x i64> @test_uqsub_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) { 262 ; CHECK: test_uqsub_v1i64: 263 %tmp1 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs) 264 ; CHECK: uqsub d0, d0, d1 265 ret <1 x i64> %tmp1 266 } 267 268 define <1 x i64> @test_sqsub_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) { 269 ; CHECK: test_sqsub_v1i64: 270 %tmp1 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %lhs, <1 x i64> %rhs) 271 ; CHECK: sqsub d0, d0, d1 272 ret <1 x i64> %tmp1 273 } 274 275
