1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s 2 ; Generate MemOps for V4 and above. 3 4 define void @memop_unsigned_char_add5(i8* nocapture %p) nounwind { 5 entry: 6 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 7 %0 = load i8* %p, align 1, !tbaa !0 8 %conv = zext i8 %0 to i32 9 %add = add nsw i32 %conv, 5 10 %conv1 = trunc i32 %add to i8 11 store i8 %conv1, i8* %p, align 1, !tbaa !0 12 ret void 13 } 14 15 define void @memop_unsigned_char_add(i8* nocapture %p, i8 zeroext %x) nounwind { 16 entry: 17 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 18 %conv = zext i8 %x to i32 19 %0 = load i8* %p, align 1, !tbaa !0 20 %conv1 = zext i8 %0 to i32 21 %add = add nsw i32 %conv1, %conv 22 %conv2 = trunc i32 %add to i8 23 store i8 %conv2, i8* %p, align 1, !tbaa !0 24 ret void 25 } 26 27 define void @memop_unsigned_char_sub(i8* nocapture %p, i8 zeroext %x) nounwind { 28 entry: 29 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 30 %conv = zext i8 %x to i32 31 %0 = load i8* %p, align 1, !tbaa !0 32 %conv1 = zext i8 %0 to i32 33 %sub = sub nsw i32 %conv1, %conv 34 %conv2 = trunc i32 %sub to i8 35 store i8 %conv2, i8* %p, align 1, !tbaa !0 36 ret void 37 } 38 39 define void @memop_unsigned_char_or(i8* nocapture %p, i8 zeroext %x) nounwind { 40 entry: 41 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 42 %0 = load i8* %p, align 1, !tbaa !0 43 %or3 = or i8 %0, %x 44 store i8 %or3, i8* %p, align 1, !tbaa !0 45 ret void 46 } 47 48 define void @memop_unsigned_char_and(i8* nocapture %p, i8 zeroext %x) nounwind { 49 entry: 50 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 51 %0 = load i8* %p, align 1, !tbaa !0 52 %and3 = and i8 %0, %x 53 store i8 %and3, i8* %p, align 1, !tbaa !0 54 ret void 55 } 56 57 define void @memop_unsigned_char_clrbit(i8* nocapture %p) nounwind { 58 entry: 59 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 60 %0 = load i8* %p, align 1, !tbaa !0 61 %conv = zext i8 %0 to i32 62 %and = and i32 %conv, 223 63 %conv1 = trunc i32 %and to i8 64 store i8 %conv1, i8* %p, align 1, !tbaa !0 65 ret void 66 } 67 68 define void @memop_unsigned_char_setbit(i8* nocapture %p) nounwind { 69 entry: 70 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 71 %0 = load i8* %p, align 1, !tbaa !0 72 %conv = zext i8 %0 to i32 73 %or = or i32 %conv, 128 74 %conv1 = trunc i32 %or to i8 75 store i8 %conv1, i8* %p, align 1, !tbaa !0 76 ret void 77 } 78 79 define void @memop_unsigned_char_add5_index(i8* nocapture %p, i32 %i) nounwind { 80 entry: 81 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 82 %add.ptr = getelementptr inbounds i8* %p, i32 %i 83 %0 = load i8* %add.ptr, align 1, !tbaa !0 84 %conv = zext i8 %0 to i32 85 %add = add nsw i32 %conv, 5 86 %conv1 = trunc i32 %add to i8 87 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 88 ret void 89 } 90 91 define void @memop_unsigned_char_add_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { 92 entry: 93 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 94 %conv = zext i8 %x to i32 95 %add.ptr = getelementptr inbounds i8* %p, i32 %i 96 %0 = load i8* %add.ptr, align 1, !tbaa !0 97 %conv1 = zext i8 %0 to i32 98 %add = add nsw i32 %conv1, %conv 99 %conv2 = trunc i32 %add to i8 100 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 101 ret void 102 } 103 104 define void @memop_unsigned_char_sub_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { 105 entry: 106 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 107 %conv = zext i8 %x to i32 108 %add.ptr = getelementptr inbounds i8* %p, i32 %i 109 %0 = load i8* %add.ptr, align 1, !tbaa !0 110 %conv1 = zext i8 %0 to i32 111 %sub = sub nsw i32 %conv1, %conv 112 %conv2 = trunc i32 %sub to i8 113 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 114 ret void 115 } 116 117 define void @memop_unsigned_char_or_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { 118 entry: 119 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 120 %add.ptr = getelementptr inbounds i8* %p, i32 %i 121 %0 = load i8* %add.ptr, align 1, !tbaa !0 122 %or3 = or i8 %0, %x 123 store i8 %or3, i8* %add.ptr, align 1, !tbaa !0 124 ret void 125 } 126 127 define void @memop_unsigned_char_and_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { 128 entry: 129 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 130 %add.ptr = getelementptr inbounds i8* %p, i32 %i 131 %0 = load i8* %add.ptr, align 1, !tbaa !0 132 %and3 = and i8 %0, %x 133 store i8 %and3, i8* %add.ptr, align 1, !tbaa !0 134 ret void 135 } 136 137 define void @memop_unsigned_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { 138 entry: 139 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 140 %add.ptr = getelementptr inbounds i8* %p, i32 %i 141 %0 = load i8* %add.ptr, align 1, !tbaa !0 142 %conv = zext i8 %0 to i32 143 %and = and i32 %conv, 223 144 %conv1 = trunc i32 %and to i8 145 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 146 ret void 147 } 148 149 define void @memop_unsigned_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { 150 entry: 151 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 152 %add.ptr = getelementptr inbounds i8* %p, i32 %i 153 %0 = load i8* %add.ptr, align 1, !tbaa !0 154 %conv = zext i8 %0 to i32 155 %or = or i32 %conv, 128 156 %conv1 = trunc i32 %or to i8 157 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 158 ret void 159 } 160 161 define void @memop_unsigned_char_add5_index5(i8* nocapture %p) nounwind { 162 entry: 163 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 164 %add.ptr = getelementptr inbounds i8* %p, i32 5 165 %0 = load i8* %add.ptr, align 1, !tbaa !0 166 %conv = zext i8 %0 to i32 167 %add = add nsw i32 %conv, 5 168 %conv1 = trunc i32 %add to i8 169 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 170 ret void 171 } 172 173 define void @memop_unsigned_char_add_index5(i8* nocapture %p, i8 zeroext %x) nounwind { 174 entry: 175 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} 176 %conv = zext i8 %x to i32 177 %add.ptr = getelementptr inbounds i8* %p, i32 5 178 %0 = load i8* %add.ptr, align 1, !tbaa !0 179 %conv1 = zext i8 %0 to i32 180 %add = add nsw i32 %conv1, %conv 181 %conv2 = trunc i32 %add to i8 182 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 183 ret void 184 } 185 186 define void @memop_unsigned_char_sub_index5(i8* nocapture %p, i8 zeroext %x) nounwind { 187 entry: 188 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} 189 %conv = zext i8 %x to i32 190 %add.ptr = getelementptr inbounds i8* %p, i32 5 191 %0 = load i8* %add.ptr, align 1, !tbaa !0 192 %conv1 = zext i8 %0 to i32 193 %sub = sub nsw i32 %conv1, %conv 194 %conv2 = trunc i32 %sub to i8 195 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 196 ret void 197 } 198 199 define void @memop_unsigned_char_or_index5(i8* nocapture %p, i8 zeroext %x) nounwind { 200 entry: 201 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} 202 %add.ptr = getelementptr inbounds i8* %p, i32 5 203 %0 = load i8* %add.ptr, align 1, !tbaa !0 204 %or3 = or i8 %0, %x 205 store i8 %or3, i8* %add.ptr, align 1, !tbaa !0 206 ret void 207 } 208 209 define void @memop_unsigned_char_and_index5(i8* nocapture %p, i8 zeroext %x) nounwind { 210 entry: 211 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} 212 %add.ptr = getelementptr inbounds i8* %p, i32 5 213 %0 = load i8* %add.ptr, align 1, !tbaa !0 214 %and3 = and i8 %0, %x 215 store i8 %and3, i8* %add.ptr, align 1, !tbaa !0 216 ret void 217 } 218 219 define void @memop_unsigned_char_clrbit_index5(i8* nocapture %p) nounwind { 220 entry: 221 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 222 %add.ptr = getelementptr inbounds i8* %p, i32 5 223 %0 = load i8* %add.ptr, align 1, !tbaa !0 224 %conv = zext i8 %0 to i32 225 %and = and i32 %conv, 223 226 %conv1 = trunc i32 %and to i8 227 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 228 ret void 229 } 230 231 define void @memop_unsigned_char_setbit_index5(i8* nocapture %p) nounwind { 232 entry: 233 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 234 %add.ptr = getelementptr inbounds i8* %p, i32 5 235 %0 = load i8* %add.ptr, align 1, !tbaa !0 236 %conv = zext i8 %0 to i32 237 %or = or i32 %conv, 128 238 %conv1 = trunc i32 %or to i8 239 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 240 ret void 241 } 242 243 define void @memop_signed_char_add5(i8* nocapture %p) nounwind { 244 entry: 245 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 246 %0 = load i8* %p, align 1, !tbaa !0 247 %conv2 = zext i8 %0 to i32 248 %add = add nsw i32 %conv2, 5 249 %conv1 = trunc i32 %add to i8 250 store i8 %conv1, i8* %p, align 1, !tbaa !0 251 ret void 252 } 253 254 define void @memop_signed_char_add(i8* nocapture %p, i8 signext %x) nounwind { 255 entry: 256 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 257 %conv4 = zext i8 %x to i32 258 %0 = load i8* %p, align 1, !tbaa !0 259 %conv13 = zext i8 %0 to i32 260 %add = add nsw i32 %conv13, %conv4 261 %conv2 = trunc i32 %add to i8 262 store i8 %conv2, i8* %p, align 1, !tbaa !0 263 ret void 264 } 265 266 define void @memop_signed_char_sub(i8* nocapture %p, i8 signext %x) nounwind { 267 entry: 268 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 269 %conv4 = zext i8 %x to i32 270 %0 = load i8* %p, align 1, !tbaa !0 271 %conv13 = zext i8 %0 to i32 272 %sub = sub nsw i32 %conv13, %conv4 273 %conv2 = trunc i32 %sub to i8 274 store i8 %conv2, i8* %p, align 1, !tbaa !0 275 ret void 276 } 277 278 define void @memop_signed_char_or(i8* nocapture %p, i8 signext %x) nounwind { 279 entry: 280 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 281 %0 = load i8* %p, align 1, !tbaa !0 282 %or3 = or i8 %0, %x 283 store i8 %or3, i8* %p, align 1, !tbaa !0 284 ret void 285 } 286 287 define void @memop_signed_char_and(i8* nocapture %p, i8 signext %x) nounwind { 288 entry: 289 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 290 %0 = load i8* %p, align 1, !tbaa !0 291 %and3 = and i8 %0, %x 292 store i8 %and3, i8* %p, align 1, !tbaa !0 293 ret void 294 } 295 296 define void @memop_signed_char_clrbit(i8* nocapture %p) nounwind { 297 entry: 298 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 299 %0 = load i8* %p, align 1, !tbaa !0 300 %conv2 = zext i8 %0 to i32 301 %and = and i32 %conv2, 223 302 %conv1 = trunc i32 %and to i8 303 store i8 %conv1, i8* %p, align 1, !tbaa !0 304 ret void 305 } 306 307 define void @memop_signed_char_setbit(i8* nocapture %p) nounwind { 308 entry: 309 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 310 %0 = load i8* %p, align 1, !tbaa !0 311 %conv2 = zext i8 %0 to i32 312 %or = or i32 %conv2, 128 313 %conv1 = trunc i32 %or to i8 314 store i8 %conv1, i8* %p, align 1, !tbaa !0 315 ret void 316 } 317 318 define void @memop_signed_char_add5_index(i8* nocapture %p, i32 %i) nounwind { 319 entry: 320 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 321 %add.ptr = getelementptr inbounds i8* %p, i32 %i 322 %0 = load i8* %add.ptr, align 1, !tbaa !0 323 %conv2 = zext i8 %0 to i32 324 %add = add nsw i32 %conv2, 5 325 %conv1 = trunc i32 %add to i8 326 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 327 ret void 328 } 329 330 define void @memop_signed_char_add_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { 331 entry: 332 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 333 %conv4 = zext i8 %x to i32 334 %add.ptr = getelementptr inbounds i8* %p, i32 %i 335 %0 = load i8* %add.ptr, align 1, !tbaa !0 336 %conv13 = zext i8 %0 to i32 337 %add = add nsw i32 %conv13, %conv4 338 %conv2 = trunc i32 %add to i8 339 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 340 ret void 341 } 342 343 define void @memop_signed_char_sub_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { 344 entry: 345 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 346 %conv4 = zext i8 %x to i32 347 %add.ptr = getelementptr inbounds i8* %p, i32 %i 348 %0 = load i8* %add.ptr, align 1, !tbaa !0 349 %conv13 = zext i8 %0 to i32 350 %sub = sub nsw i32 %conv13, %conv4 351 %conv2 = trunc i32 %sub to i8 352 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 353 ret void 354 } 355 356 define void @memop_signed_char_or_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { 357 entry: 358 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 359 %add.ptr = getelementptr inbounds i8* %p, i32 %i 360 %0 = load i8* %add.ptr, align 1, !tbaa !0 361 %or3 = or i8 %0, %x 362 store i8 %or3, i8* %add.ptr, align 1, !tbaa !0 363 ret void 364 } 365 366 define void @memop_signed_char_and_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { 367 entry: 368 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 369 %add.ptr = getelementptr inbounds i8* %p, i32 %i 370 %0 = load i8* %add.ptr, align 1, !tbaa !0 371 %and3 = and i8 %0, %x 372 store i8 %and3, i8* %add.ptr, align 1, !tbaa !0 373 ret void 374 } 375 376 define void @memop_signed_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { 377 entry: 378 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 379 %add.ptr = getelementptr inbounds i8* %p, i32 %i 380 %0 = load i8* %add.ptr, align 1, !tbaa !0 381 %conv2 = zext i8 %0 to i32 382 %and = and i32 %conv2, 223 383 %conv1 = trunc i32 %and to i8 384 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 385 ret void 386 } 387 388 define void @memop_signed_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { 389 entry: 390 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 391 %add.ptr = getelementptr inbounds i8* %p, i32 %i 392 %0 = load i8* %add.ptr, align 1, !tbaa !0 393 %conv2 = zext i8 %0 to i32 394 %or = or i32 %conv2, 128 395 %conv1 = trunc i32 %or to i8 396 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 397 ret void 398 } 399 400 define void @memop_signed_char_add5_index5(i8* nocapture %p) nounwind { 401 entry: 402 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 403 %add.ptr = getelementptr inbounds i8* %p, i32 5 404 %0 = load i8* %add.ptr, align 1, !tbaa !0 405 %conv2 = zext i8 %0 to i32 406 %add = add nsw i32 %conv2, 5 407 %conv1 = trunc i32 %add to i8 408 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 409 ret void 410 } 411 412 define void @memop_signed_char_add_index5(i8* nocapture %p, i8 signext %x) nounwind { 413 entry: 414 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} 415 %conv4 = zext i8 %x to i32 416 %add.ptr = getelementptr inbounds i8* %p, i32 5 417 %0 = load i8* %add.ptr, align 1, !tbaa !0 418 %conv13 = zext i8 %0 to i32 419 %add = add nsw i32 %conv13, %conv4 420 %conv2 = trunc i32 %add to i8 421 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 422 ret void 423 } 424 425 define void @memop_signed_char_sub_index5(i8* nocapture %p, i8 signext %x) nounwind { 426 entry: 427 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} 428 %conv4 = zext i8 %x to i32 429 %add.ptr = getelementptr inbounds i8* %p, i32 5 430 %0 = load i8* %add.ptr, align 1, !tbaa !0 431 %conv13 = zext i8 %0 to i32 432 %sub = sub nsw i32 %conv13, %conv4 433 %conv2 = trunc i32 %sub to i8 434 store i8 %conv2, i8* %add.ptr, align 1, !tbaa !0 435 ret void 436 } 437 438 define void @memop_signed_char_or_index5(i8* nocapture %p, i8 signext %x) nounwind { 439 entry: 440 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} 441 %add.ptr = getelementptr inbounds i8* %p, i32 5 442 %0 = load i8* %add.ptr, align 1, !tbaa !0 443 %or3 = or i8 %0, %x 444 store i8 %or3, i8* %add.ptr, align 1, !tbaa !0 445 ret void 446 } 447 448 define void @memop_signed_char_and_index5(i8* nocapture %p, i8 signext %x) nounwind { 449 entry: 450 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} 451 %add.ptr = getelementptr inbounds i8* %p, i32 5 452 %0 = load i8* %add.ptr, align 1, !tbaa !0 453 %and3 = and i8 %0, %x 454 store i8 %and3, i8* %add.ptr, align 1, !tbaa !0 455 ret void 456 } 457 458 define void @memop_signed_char_clrbit_index5(i8* nocapture %p) nounwind { 459 entry: 460 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 461 %add.ptr = getelementptr inbounds i8* %p, i32 5 462 %0 = load i8* %add.ptr, align 1, !tbaa !0 463 %conv2 = zext i8 %0 to i32 464 %and = and i32 %conv2, 223 465 %conv1 = trunc i32 %and to i8 466 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 467 ret void 468 } 469 470 define void @memop_signed_char_setbit_index5(i8* nocapture %p) nounwind { 471 entry: 472 ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 473 %add.ptr = getelementptr inbounds i8* %p, i32 5 474 %0 = load i8* %add.ptr, align 1, !tbaa !0 475 %conv2 = zext i8 %0 to i32 476 %or = or i32 %conv2, 128 477 %conv1 = trunc i32 %or to i8 478 store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 479 ret void 480 } 481 482 define void @memop_unsigned_short_add5(i16* nocapture %p) nounwind { 483 entry: 484 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 485 %0 = load i16* %p, align 2, !tbaa !2 486 %conv = zext i16 %0 to i32 487 %add = add nsw i32 %conv, 5 488 %conv1 = trunc i32 %add to i16 489 store i16 %conv1, i16* %p, align 2, !tbaa !2 490 ret void 491 } 492 493 define void @memop_unsigned_short_add(i16* nocapture %p, i16 zeroext %x) nounwind { 494 entry: 495 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 496 %conv = zext i16 %x to i32 497 %0 = load i16* %p, align 2, !tbaa !2 498 %conv1 = zext i16 %0 to i32 499 %add = add nsw i32 %conv1, %conv 500 %conv2 = trunc i32 %add to i16 501 store i16 %conv2, i16* %p, align 2, !tbaa !2 502 ret void 503 } 504 505 define void @memop_unsigned_short_sub(i16* nocapture %p, i16 zeroext %x) nounwind { 506 entry: 507 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 508 %conv = zext i16 %x to i32 509 %0 = load i16* %p, align 2, !tbaa !2 510 %conv1 = zext i16 %0 to i32 511 %sub = sub nsw i32 %conv1, %conv 512 %conv2 = trunc i32 %sub to i16 513 store i16 %conv2, i16* %p, align 2, !tbaa !2 514 ret void 515 } 516 517 define void @memop_unsigned_short_or(i16* nocapture %p, i16 zeroext %x) nounwind { 518 entry: 519 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 520 %0 = load i16* %p, align 2, !tbaa !2 521 %or3 = or i16 %0, %x 522 store i16 %or3, i16* %p, align 2, !tbaa !2 523 ret void 524 } 525 526 define void @memop_unsigned_short_and(i16* nocapture %p, i16 zeroext %x) nounwind { 527 entry: 528 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 529 %0 = load i16* %p, align 2, !tbaa !2 530 %and3 = and i16 %0, %x 531 store i16 %and3, i16* %p, align 2, !tbaa !2 532 ret void 533 } 534 535 define void @memop_unsigned_short_clrbit(i16* nocapture %p) nounwind { 536 entry: 537 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 538 %0 = load i16* %p, align 2, !tbaa !2 539 %conv = zext i16 %0 to i32 540 %and = and i32 %conv, 65503 541 %conv1 = trunc i32 %and to i16 542 store i16 %conv1, i16* %p, align 2, !tbaa !2 543 ret void 544 } 545 546 define void @memop_unsigned_short_setbit(i16* nocapture %p) nounwind { 547 entry: 548 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 549 %0 = load i16* %p, align 2, !tbaa !2 550 %conv = zext i16 %0 to i32 551 %or = or i32 %conv, 128 552 %conv1 = trunc i32 %or to i16 553 store i16 %conv1, i16* %p, align 2, !tbaa !2 554 ret void 555 } 556 557 define void @memop_unsigned_short_add5_index(i16* nocapture %p, i32 %i) nounwind { 558 entry: 559 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 560 %add.ptr = getelementptr inbounds i16* %p, i32 %i 561 %0 = load i16* %add.ptr, align 2, !tbaa !2 562 %conv = zext i16 %0 to i32 563 %add = add nsw i32 %conv, 5 564 %conv1 = trunc i32 %add to i16 565 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 566 ret void 567 } 568 569 define void @memop_unsigned_short_add_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { 570 entry: 571 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 572 %conv = zext i16 %x to i32 573 %add.ptr = getelementptr inbounds i16* %p, i32 %i 574 %0 = load i16* %add.ptr, align 2, !tbaa !2 575 %conv1 = zext i16 %0 to i32 576 %add = add nsw i32 %conv1, %conv 577 %conv2 = trunc i32 %add to i16 578 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 579 ret void 580 } 581 582 define void @memop_unsigned_short_sub_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { 583 entry: 584 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 585 %conv = zext i16 %x to i32 586 %add.ptr = getelementptr inbounds i16* %p, i32 %i 587 %0 = load i16* %add.ptr, align 2, !tbaa !2 588 %conv1 = zext i16 %0 to i32 589 %sub = sub nsw i32 %conv1, %conv 590 %conv2 = trunc i32 %sub to i16 591 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 592 ret void 593 } 594 595 define void @memop_unsigned_short_or_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { 596 entry: 597 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 598 %add.ptr = getelementptr inbounds i16* %p, i32 %i 599 %0 = load i16* %add.ptr, align 2, !tbaa !2 600 %or3 = or i16 %0, %x 601 store i16 %or3, i16* %add.ptr, align 2, !tbaa !2 602 ret void 603 } 604 605 define void @memop_unsigned_short_and_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { 606 entry: 607 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 608 %add.ptr = getelementptr inbounds i16* %p, i32 %i 609 %0 = load i16* %add.ptr, align 2, !tbaa !2 610 %and3 = and i16 %0, %x 611 store i16 %and3, i16* %add.ptr, align 2, !tbaa !2 612 ret void 613 } 614 615 define void @memop_unsigned_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { 616 entry: 617 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 618 %add.ptr = getelementptr inbounds i16* %p, i32 %i 619 %0 = load i16* %add.ptr, align 2, !tbaa !2 620 %conv = zext i16 %0 to i32 621 %and = and i32 %conv, 65503 622 %conv1 = trunc i32 %and to i16 623 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 624 ret void 625 } 626 627 define void @memop_unsigned_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { 628 entry: 629 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 630 %add.ptr = getelementptr inbounds i16* %p, i32 %i 631 %0 = load i16* %add.ptr, align 2, !tbaa !2 632 %conv = zext i16 %0 to i32 633 %or = or i32 %conv, 128 634 %conv1 = trunc i32 %or to i16 635 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 636 ret void 637 } 638 639 define void @memop_unsigned_short_add5_index5(i16* nocapture %p) nounwind { 640 entry: 641 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 642 %add.ptr = getelementptr inbounds i16* %p, i32 5 643 %0 = load i16* %add.ptr, align 2, !tbaa !2 644 %conv = zext i16 %0 to i32 645 %add = add nsw i32 %conv, 5 646 %conv1 = trunc i32 %add to i16 647 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 648 ret void 649 } 650 651 define void @memop_unsigned_short_add_index5(i16* nocapture %p, i16 zeroext %x) nounwind { 652 entry: 653 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} 654 %conv = zext i16 %x to i32 655 %add.ptr = getelementptr inbounds i16* %p, i32 5 656 %0 = load i16* %add.ptr, align 2, !tbaa !2 657 %conv1 = zext i16 %0 to i32 658 %add = add nsw i32 %conv1, %conv 659 %conv2 = trunc i32 %add to i16 660 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 661 ret void 662 } 663 664 define void @memop_unsigned_short_sub_index5(i16* nocapture %p, i16 zeroext %x) nounwind { 665 entry: 666 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} 667 %conv = zext i16 %x to i32 668 %add.ptr = getelementptr inbounds i16* %p, i32 5 669 %0 = load i16* %add.ptr, align 2, !tbaa !2 670 %conv1 = zext i16 %0 to i32 671 %sub = sub nsw i32 %conv1, %conv 672 %conv2 = trunc i32 %sub to i16 673 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 674 ret void 675 } 676 677 define void @memop_unsigned_short_or_index5(i16* nocapture %p, i16 zeroext %x) nounwind { 678 entry: 679 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} 680 %add.ptr = getelementptr inbounds i16* %p, i32 5 681 %0 = load i16* %add.ptr, align 2, !tbaa !2 682 %or3 = or i16 %0, %x 683 store i16 %or3, i16* %add.ptr, align 2, !tbaa !2 684 ret void 685 } 686 687 define void @memop_unsigned_short_and_index5(i16* nocapture %p, i16 zeroext %x) nounwind { 688 entry: 689 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} 690 %add.ptr = getelementptr inbounds i16* %p, i32 5 691 %0 = load i16* %add.ptr, align 2, !tbaa !2 692 %and3 = and i16 %0, %x 693 store i16 %and3, i16* %add.ptr, align 2, !tbaa !2 694 ret void 695 } 696 697 define void @memop_unsigned_short_clrbit_index5(i16* nocapture %p) nounwind { 698 entry: 699 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 700 %add.ptr = getelementptr inbounds i16* %p, i32 5 701 %0 = load i16* %add.ptr, align 2, !tbaa !2 702 %conv = zext i16 %0 to i32 703 %and = and i32 %conv, 65503 704 %conv1 = trunc i32 %and to i16 705 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 706 ret void 707 } 708 709 define void @memop_unsigned_short_setbit_index5(i16* nocapture %p) nounwind { 710 entry: 711 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 712 %add.ptr = getelementptr inbounds i16* %p, i32 5 713 %0 = load i16* %add.ptr, align 2, !tbaa !2 714 %conv = zext i16 %0 to i32 715 %or = or i32 %conv, 128 716 %conv1 = trunc i32 %or to i16 717 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 718 ret void 719 } 720 721 define void @memop_signed_short_add5(i16* nocapture %p) nounwind { 722 entry: 723 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 724 %0 = load i16* %p, align 2, !tbaa !2 725 %conv2 = zext i16 %0 to i32 726 %add = add nsw i32 %conv2, 5 727 %conv1 = trunc i32 %add to i16 728 store i16 %conv1, i16* %p, align 2, !tbaa !2 729 ret void 730 } 731 732 define void @memop_signed_short_add(i16* nocapture %p, i16 signext %x) nounwind { 733 entry: 734 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 735 %conv4 = zext i16 %x to i32 736 %0 = load i16* %p, align 2, !tbaa !2 737 %conv13 = zext i16 %0 to i32 738 %add = add nsw i32 %conv13, %conv4 739 %conv2 = trunc i32 %add to i16 740 store i16 %conv2, i16* %p, align 2, !tbaa !2 741 ret void 742 } 743 744 define void @memop_signed_short_sub(i16* nocapture %p, i16 signext %x) nounwind { 745 entry: 746 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 747 %conv4 = zext i16 %x to i32 748 %0 = load i16* %p, align 2, !tbaa !2 749 %conv13 = zext i16 %0 to i32 750 %sub = sub nsw i32 %conv13, %conv4 751 %conv2 = trunc i32 %sub to i16 752 store i16 %conv2, i16* %p, align 2, !tbaa !2 753 ret void 754 } 755 756 define void @memop_signed_short_or(i16* nocapture %p, i16 signext %x) nounwind { 757 entry: 758 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 759 %0 = load i16* %p, align 2, !tbaa !2 760 %or3 = or i16 %0, %x 761 store i16 %or3, i16* %p, align 2, !tbaa !2 762 ret void 763 } 764 765 define void @memop_signed_short_and(i16* nocapture %p, i16 signext %x) nounwind { 766 entry: 767 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 768 %0 = load i16* %p, align 2, !tbaa !2 769 %and3 = and i16 %0, %x 770 store i16 %and3, i16* %p, align 2, !tbaa !2 771 ret void 772 } 773 774 define void @memop_signed_short_clrbit(i16* nocapture %p) nounwind { 775 entry: 776 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 777 %0 = load i16* %p, align 2, !tbaa !2 778 %conv2 = zext i16 %0 to i32 779 %and = and i32 %conv2, 65503 780 %conv1 = trunc i32 %and to i16 781 store i16 %conv1, i16* %p, align 2, !tbaa !2 782 ret void 783 } 784 785 define void @memop_signed_short_setbit(i16* nocapture %p) nounwind { 786 entry: 787 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 788 %0 = load i16* %p, align 2, !tbaa !2 789 %conv2 = zext i16 %0 to i32 790 %or = or i32 %conv2, 128 791 %conv1 = trunc i32 %or to i16 792 store i16 %conv1, i16* %p, align 2, !tbaa !2 793 ret void 794 } 795 796 define void @memop_signed_short_add5_index(i16* nocapture %p, i32 %i) nounwind { 797 entry: 798 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 799 %add.ptr = getelementptr inbounds i16* %p, i32 %i 800 %0 = load i16* %add.ptr, align 2, !tbaa !2 801 %conv2 = zext i16 %0 to i32 802 %add = add nsw i32 %conv2, 5 803 %conv1 = trunc i32 %add to i16 804 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 805 ret void 806 } 807 808 define void @memop_signed_short_add_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { 809 entry: 810 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 811 %conv4 = zext i16 %x to i32 812 %add.ptr = getelementptr inbounds i16* %p, i32 %i 813 %0 = load i16* %add.ptr, align 2, !tbaa !2 814 %conv13 = zext i16 %0 to i32 815 %add = add nsw i32 %conv13, %conv4 816 %conv2 = trunc i32 %add to i16 817 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 818 ret void 819 } 820 821 define void @memop_signed_short_sub_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { 822 entry: 823 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 824 %conv4 = zext i16 %x to i32 825 %add.ptr = getelementptr inbounds i16* %p, i32 %i 826 %0 = load i16* %add.ptr, align 2, !tbaa !2 827 %conv13 = zext i16 %0 to i32 828 %sub = sub nsw i32 %conv13, %conv4 829 %conv2 = trunc i32 %sub to i16 830 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 831 ret void 832 } 833 834 define void @memop_signed_short_or_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { 835 entry: 836 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 837 %add.ptr = getelementptr inbounds i16* %p, i32 %i 838 %0 = load i16* %add.ptr, align 2, !tbaa !2 839 %or3 = or i16 %0, %x 840 store i16 %or3, i16* %add.ptr, align 2, !tbaa !2 841 ret void 842 } 843 844 define void @memop_signed_short_and_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { 845 entry: 846 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 847 %add.ptr = getelementptr inbounds i16* %p, i32 %i 848 %0 = load i16* %add.ptr, align 2, !tbaa !2 849 %and3 = and i16 %0, %x 850 store i16 %and3, i16* %add.ptr, align 2, !tbaa !2 851 ret void 852 } 853 854 define void @memop_signed_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { 855 entry: 856 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 857 %add.ptr = getelementptr inbounds i16* %p, i32 %i 858 %0 = load i16* %add.ptr, align 2, !tbaa !2 859 %conv2 = zext i16 %0 to i32 860 %and = and i32 %conv2, 65503 861 %conv1 = trunc i32 %and to i16 862 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 863 ret void 864 } 865 866 define void @memop_signed_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { 867 entry: 868 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 869 %add.ptr = getelementptr inbounds i16* %p, i32 %i 870 %0 = load i16* %add.ptr, align 2, !tbaa !2 871 %conv2 = zext i16 %0 to i32 872 %or = or i32 %conv2, 128 873 %conv1 = trunc i32 %or to i16 874 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 875 ret void 876 } 877 878 define void @memop_signed_short_add5_index5(i16* nocapture %p) nounwind { 879 entry: 880 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 881 %add.ptr = getelementptr inbounds i16* %p, i32 5 882 %0 = load i16* %add.ptr, align 2, !tbaa !2 883 %conv2 = zext i16 %0 to i32 884 %add = add nsw i32 %conv2, 5 885 %conv1 = trunc i32 %add to i16 886 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 887 ret void 888 } 889 890 define void @memop_signed_short_add_index5(i16* nocapture %p, i16 signext %x) nounwind { 891 entry: 892 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} 893 %conv4 = zext i16 %x to i32 894 %add.ptr = getelementptr inbounds i16* %p, i32 5 895 %0 = load i16* %add.ptr, align 2, !tbaa !2 896 %conv13 = zext i16 %0 to i32 897 %add = add nsw i32 %conv13, %conv4 898 %conv2 = trunc i32 %add to i16 899 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 900 ret void 901 } 902 903 define void @memop_signed_short_sub_index5(i16* nocapture %p, i16 signext %x) nounwind { 904 entry: 905 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} 906 %conv4 = zext i16 %x to i32 907 %add.ptr = getelementptr inbounds i16* %p, i32 5 908 %0 = load i16* %add.ptr, align 2, !tbaa !2 909 %conv13 = zext i16 %0 to i32 910 %sub = sub nsw i32 %conv13, %conv4 911 %conv2 = trunc i32 %sub to i16 912 store i16 %conv2, i16* %add.ptr, align 2, !tbaa !2 913 ret void 914 } 915 916 define void @memop_signed_short_or_index5(i16* nocapture %p, i16 signext %x) nounwind { 917 entry: 918 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} 919 %add.ptr = getelementptr inbounds i16* %p, i32 5 920 %0 = load i16* %add.ptr, align 2, !tbaa !2 921 %or3 = or i16 %0, %x 922 store i16 %or3, i16* %add.ptr, align 2, !tbaa !2 923 ret void 924 } 925 926 define void @memop_signed_short_and_index5(i16* nocapture %p, i16 signext %x) nounwind { 927 entry: 928 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} 929 %add.ptr = getelementptr inbounds i16* %p, i32 5 930 %0 = load i16* %add.ptr, align 2, !tbaa !2 931 %and3 = and i16 %0, %x 932 store i16 %and3, i16* %add.ptr, align 2, !tbaa !2 933 ret void 934 } 935 936 define void @memop_signed_short_clrbit_index5(i16* nocapture %p) nounwind { 937 entry: 938 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 939 %add.ptr = getelementptr inbounds i16* %p, i32 5 940 %0 = load i16* %add.ptr, align 2, !tbaa !2 941 %conv2 = zext i16 %0 to i32 942 %and = and i32 %conv2, 65503 943 %conv1 = trunc i32 %and to i16 944 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 945 ret void 946 } 947 948 define void @memop_signed_short_setbit_index5(i16* nocapture %p) nounwind { 949 entry: 950 ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 951 %add.ptr = getelementptr inbounds i16* %p, i32 5 952 %0 = load i16* %add.ptr, align 2, !tbaa !2 953 %conv2 = zext i16 %0 to i32 954 %or = or i32 %conv2, 128 955 %conv1 = trunc i32 %or to i16 956 store i16 %conv1, i16* %add.ptr, align 2, !tbaa !2 957 ret void 958 } 959 960 define void @memop_signed_int_add5(i32* nocapture %p) nounwind { 961 entry: 962 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 963 %0 = load i32* %p, align 4, !tbaa !3 964 %add = add i32 %0, 5 965 store i32 %add, i32* %p, align 4, !tbaa !3 966 ret void 967 } 968 969 define void @memop_signed_int_add(i32* nocapture %p, i32 %x) nounwind { 970 entry: 971 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 972 %0 = load i32* %p, align 4, !tbaa !3 973 %add = add i32 %0, %x 974 store i32 %add, i32* %p, align 4, !tbaa !3 975 ret void 976 } 977 978 define void @memop_signed_int_sub(i32* nocapture %p, i32 %x) nounwind { 979 entry: 980 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 981 %0 = load i32* %p, align 4, !tbaa !3 982 %sub = sub i32 %0, %x 983 store i32 %sub, i32* %p, align 4, !tbaa !3 984 ret void 985 } 986 987 define void @memop_signed_int_or(i32* nocapture %p, i32 %x) nounwind { 988 entry: 989 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 990 %0 = load i32* %p, align 4, !tbaa !3 991 %or = or i32 %0, %x 992 store i32 %or, i32* %p, align 4, !tbaa !3 993 ret void 994 } 995 996 define void @memop_signed_int_and(i32* nocapture %p, i32 %x) nounwind { 997 entry: 998 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 999 %0 = load i32* %p, align 4, !tbaa !3 1000 %and = and i32 %0, %x 1001 store i32 %and, i32* %p, align 4, !tbaa !3 1002 ret void 1003 } 1004 1005 define void @memop_signed_int_clrbit(i32* nocapture %p) nounwind { 1006 entry: 1007 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 1008 %0 = load i32* %p, align 4, !tbaa !3 1009 %and = and i32 %0, -33 1010 store i32 %and, i32* %p, align 4, !tbaa !3 1011 ret void 1012 } 1013 1014 define void @memop_signed_int_setbit(i32* nocapture %p) nounwind { 1015 entry: 1016 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 1017 %0 = load i32* %p, align 4, !tbaa !3 1018 %or = or i32 %0, 128 1019 store i32 %or, i32* %p, align 4, !tbaa !3 1020 ret void 1021 } 1022 1023 define void @memop_signed_int_add5_index(i32* nocapture %p, i32 %i) nounwind { 1024 entry: 1025 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 1026 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1027 %0 = load i32* %add.ptr, align 4, !tbaa !3 1028 %add = add i32 %0, 5 1029 store i32 %add, i32* %add.ptr, align 4, !tbaa !3 1030 ret void 1031 } 1032 1033 define void @memop_signed_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1034 entry: 1035 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 1036 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1037 %0 = load i32* %add.ptr, align 4, !tbaa !3 1038 %add = add i32 %0, %x 1039 store i32 %add, i32* %add.ptr, align 4, !tbaa !3 1040 ret void 1041 } 1042 1043 define void @memop_signed_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1044 entry: 1045 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 1046 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1047 %0 = load i32* %add.ptr, align 4, !tbaa !3 1048 %sub = sub i32 %0, %x 1049 store i32 %sub, i32* %add.ptr, align 4, !tbaa !3 1050 ret void 1051 } 1052 1053 define void @memop_signed_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1054 entry: 1055 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 1056 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1057 %0 = load i32* %add.ptr, align 4, !tbaa !3 1058 %or = or i32 %0, %x 1059 store i32 %or, i32* %add.ptr, align 4, !tbaa !3 1060 ret void 1061 } 1062 1063 define void @memop_signed_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1064 entry: 1065 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 1066 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1067 %0 = load i32* %add.ptr, align 4, !tbaa !3 1068 %and = and i32 %0, %x 1069 store i32 %and, i32* %add.ptr, align 4, !tbaa !3 1070 ret void 1071 } 1072 1073 define void @memop_signed_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { 1074 entry: 1075 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 1076 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1077 %0 = load i32* %add.ptr, align 4, !tbaa !3 1078 %and = and i32 %0, -33 1079 store i32 %and, i32* %add.ptr, align 4, !tbaa !3 1080 ret void 1081 } 1082 1083 define void @memop_signed_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { 1084 entry: 1085 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 1086 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1087 %0 = load i32* %add.ptr, align 4, !tbaa !3 1088 %or = or i32 %0, 128 1089 store i32 %or, i32* %add.ptr, align 4, !tbaa !3 1090 ret void 1091 } 1092 1093 define void @memop_signed_int_add5_index5(i32* nocapture %p) nounwind { 1094 entry: 1095 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 1096 %add.ptr = getelementptr inbounds i32* %p, i32 5 1097 %0 = load i32* %add.ptr, align 4, !tbaa !3 1098 %add = add i32 %0, 5 1099 store i32 %add, i32* %add.ptr, align 4, !tbaa !3 1100 ret void 1101 } 1102 1103 define void @memop_signed_int_add_index5(i32* nocapture %p, i32 %x) nounwind { 1104 entry: 1105 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} 1106 %add.ptr = getelementptr inbounds i32* %p, i32 5 1107 %0 = load i32* %add.ptr, align 4, !tbaa !3 1108 %add = add i32 %0, %x 1109 store i32 %add, i32* %add.ptr, align 4, !tbaa !3 1110 ret void 1111 } 1112 1113 define void @memop_signed_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { 1114 entry: 1115 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} 1116 %add.ptr = getelementptr inbounds i32* %p, i32 5 1117 %0 = load i32* %add.ptr, align 4, !tbaa !3 1118 %sub = sub i32 %0, %x 1119 store i32 %sub, i32* %add.ptr, align 4, !tbaa !3 1120 ret void 1121 } 1122 1123 define void @memop_signed_int_or_index5(i32* nocapture %p, i32 %x) nounwind { 1124 entry: 1125 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} 1126 %add.ptr = getelementptr inbounds i32* %p, i32 5 1127 %0 = load i32* %add.ptr, align 4, !tbaa !3 1128 %or = or i32 %0, %x 1129 store i32 %or, i32* %add.ptr, align 4, !tbaa !3 1130 ret void 1131 } 1132 1133 define void @memop_signed_int_and_index5(i32* nocapture %p, i32 %x) nounwind { 1134 entry: 1135 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} 1136 %add.ptr = getelementptr inbounds i32* %p, i32 5 1137 %0 = load i32* %add.ptr, align 4, !tbaa !3 1138 %and = and i32 %0, %x 1139 store i32 %and, i32* %add.ptr, align 4, !tbaa !3 1140 ret void 1141 } 1142 1143 define void @memop_signed_int_clrbit_index5(i32* nocapture %p) nounwind { 1144 entry: 1145 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 1146 %add.ptr = getelementptr inbounds i32* %p, i32 5 1147 %0 = load i32* %add.ptr, align 4, !tbaa !3 1148 %and = and i32 %0, -33 1149 store i32 %and, i32* %add.ptr, align 4, !tbaa !3 1150 ret void 1151 } 1152 1153 define void @memop_signed_int_setbit_index5(i32* nocapture %p) nounwind { 1154 entry: 1155 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 1156 %add.ptr = getelementptr inbounds i32* %p, i32 5 1157 %0 = load i32* %add.ptr, align 4, !tbaa !3 1158 %or = or i32 %0, 128 1159 store i32 %or, i32* %add.ptr, align 4, !tbaa !3 1160 ret void 1161 } 1162 1163 define void @memop_unsigned_int_add5(i32* nocapture %p) nounwind { 1164 entry: 1165 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 1166 %0 = load i32* %p, align 4, !tbaa !3 1167 %add = add nsw i32 %0, 5 1168 store i32 %add, i32* %p, align 4, !tbaa !3 1169 ret void 1170 } 1171 1172 define void @memop_unsigned_int_add(i32* nocapture %p, i32 %x) nounwind { 1173 entry: 1174 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 1175 %0 = load i32* %p, align 4, !tbaa !3 1176 %add = add nsw i32 %0, %x 1177 store i32 %add, i32* %p, align 4, !tbaa !3 1178 ret void 1179 } 1180 1181 define void @memop_unsigned_int_sub(i32* nocapture %p, i32 %x) nounwind { 1182 entry: 1183 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 1184 %0 = load i32* %p, align 4, !tbaa !3 1185 %sub = sub nsw i32 %0, %x 1186 store i32 %sub, i32* %p, align 4, !tbaa !3 1187 ret void 1188 } 1189 1190 define void @memop_unsigned_int_or(i32* nocapture %p, i32 %x) nounwind { 1191 entry: 1192 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 1193 %0 = load i32* %p, align 4, !tbaa !3 1194 %or = or i32 %0, %x 1195 store i32 %or, i32* %p, align 4, !tbaa !3 1196 ret void 1197 } 1198 1199 define void @memop_unsigned_int_and(i32* nocapture %p, i32 %x) nounwind { 1200 entry: 1201 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 1202 %0 = load i32* %p, align 4, !tbaa !3 1203 %and = and i32 %0, %x 1204 store i32 %and, i32* %p, align 4, !tbaa !3 1205 ret void 1206 } 1207 1208 define void @memop_unsigned_int_clrbit(i32* nocapture %p) nounwind { 1209 entry: 1210 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 1211 %0 = load i32* %p, align 4, !tbaa !3 1212 %and = and i32 %0, -33 1213 store i32 %and, i32* %p, align 4, !tbaa !3 1214 ret void 1215 } 1216 1217 define void @memop_unsigned_int_setbit(i32* nocapture %p) nounwind { 1218 entry: 1219 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 1220 %0 = load i32* %p, align 4, !tbaa !3 1221 %or = or i32 %0, 128 1222 store i32 %or, i32* %p, align 4, !tbaa !3 1223 ret void 1224 } 1225 1226 define void @memop_unsigned_int_add5_index(i32* nocapture %p, i32 %i) nounwind { 1227 entry: 1228 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 1229 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1230 %0 = load i32* %add.ptr, align 4, !tbaa !3 1231 %add = add nsw i32 %0, 5 1232 store i32 %add, i32* %add.ptr, align 4, !tbaa !3 1233 ret void 1234 } 1235 1236 define void @memop_unsigned_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1237 entry: 1238 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} 1239 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1240 %0 = load i32* %add.ptr, align 4, !tbaa !3 1241 %add = add nsw i32 %0, %x 1242 store i32 %add, i32* %add.ptr, align 4, !tbaa !3 1243 ret void 1244 } 1245 1246 define void @memop_unsigned_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1247 entry: 1248 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} 1249 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1250 %0 = load i32* %add.ptr, align 4, !tbaa !3 1251 %sub = sub nsw i32 %0, %x 1252 store i32 %sub, i32* %add.ptr, align 4, !tbaa !3 1253 ret void 1254 } 1255 1256 define void @memop_unsigned_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1257 entry: 1258 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} 1259 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1260 %0 = load i32* %add.ptr, align 4, !tbaa !3 1261 %or = or i32 %0, %x 1262 store i32 %or, i32* %add.ptr, align 4, !tbaa !3 1263 ret void 1264 } 1265 1266 define void @memop_unsigned_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { 1267 entry: 1268 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} 1269 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1270 %0 = load i32* %add.ptr, align 4, !tbaa !3 1271 %and = and i32 %0, %x 1272 store i32 %and, i32* %add.ptr, align 4, !tbaa !3 1273 ret void 1274 } 1275 1276 define void @memop_unsigned_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { 1277 entry: 1278 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 1279 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1280 %0 = load i32* %add.ptr, align 4, !tbaa !3 1281 %and = and i32 %0, -33 1282 store i32 %and, i32* %add.ptr, align 4, !tbaa !3 1283 ret void 1284 } 1285 1286 define void @memop_unsigned_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { 1287 entry: 1288 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 1289 %add.ptr = getelementptr inbounds i32* %p, i32 %i 1290 %0 = load i32* %add.ptr, align 4, !tbaa !3 1291 %or = or i32 %0, 128 1292 store i32 %or, i32* %add.ptr, align 4, !tbaa !3 1293 ret void 1294 } 1295 1296 define void @memop_unsigned_int_add5_index5(i32* nocapture %p) nounwind { 1297 entry: 1298 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 1299 %add.ptr = getelementptr inbounds i32* %p, i32 5 1300 %0 = load i32* %add.ptr, align 4, !tbaa !3 1301 %add = add nsw i32 %0, 5 1302 store i32 %add, i32* %add.ptr, align 4, !tbaa !3 1303 ret void 1304 } 1305 1306 define void @memop_unsigned_int_add_index5(i32* nocapture %p, i32 %x) nounwind { 1307 entry: 1308 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} 1309 %add.ptr = getelementptr inbounds i32* %p, i32 5 1310 %0 = load i32* %add.ptr, align 4, !tbaa !3 1311 %add = add nsw i32 %0, %x 1312 store i32 %add, i32* %add.ptr, align 4, !tbaa !3 1313 ret void 1314 } 1315 1316 define void @memop_unsigned_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { 1317 entry: 1318 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} 1319 %add.ptr = getelementptr inbounds i32* %p, i32 5 1320 %0 = load i32* %add.ptr, align 4, !tbaa !3 1321 %sub = sub nsw i32 %0, %x 1322 store i32 %sub, i32* %add.ptr, align 4, !tbaa !3 1323 ret void 1324 } 1325 1326 define void @memop_unsigned_int_or_index5(i32* nocapture %p, i32 %x) nounwind { 1327 entry: 1328 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} 1329 %add.ptr = getelementptr inbounds i32* %p, i32 5 1330 %0 = load i32* %add.ptr, align 4, !tbaa !3 1331 %or = or i32 %0, %x 1332 store i32 %or, i32* %add.ptr, align 4, !tbaa !3 1333 ret void 1334 } 1335 1336 define void @memop_unsigned_int_and_index5(i32* nocapture %p, i32 %x) nounwind { 1337 entry: 1338 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} 1339 %add.ptr = getelementptr inbounds i32* %p, i32 5 1340 %0 = load i32* %add.ptr, align 4, !tbaa !3 1341 %and = and i32 %0, %x 1342 store i32 %and, i32* %add.ptr, align 4, !tbaa !3 1343 ret void 1344 } 1345 1346 define void @memop_unsigned_int_clrbit_index5(i32* nocapture %p) nounwind { 1347 entry: 1348 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) 1349 %add.ptr = getelementptr inbounds i32* %p, i32 5 1350 %0 = load i32* %add.ptr, align 4, !tbaa !3 1351 %and = and i32 %0, -33 1352 store i32 %and, i32* %add.ptr, align 4, !tbaa !3 1353 ret void 1354 } 1355 1356 define void @memop_unsigned_int_setbit_index5(i32* nocapture %p) nounwind { 1357 entry: 1358 ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) 1359 %add.ptr = getelementptr inbounds i32* %p, i32 5 1360 %0 = load i32* %add.ptr, align 4, !tbaa !3 1361 %or = or i32 %0, 128 1362 store i32 %or, i32* %add.ptr, align 4, !tbaa !3 1363 ret void 1364 } 1365 1366 !0 = metadata !{metadata !"omnipotent char", metadata !1} 1367 !1 = metadata !{metadata !"Simple C/C++ TBAA"} 1368 !2 = metadata !{metadata !"short", metadata !0} 1369 !3 = metadata !{metadata !"int", metadata !0} 1370
