1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s 2 3 ; These tests check that fdiv is expanded correctly and also test that the 4 ; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate 5 ; instruction groups. 6 7 ; CHECK: @fdiv_v2f32 8 ; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z 9 ; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y 10 ; CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS 11 ; CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS 12 define void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { 13 entry: 14 %0 = fdiv <2 x float> %a, %b 15 store <2 x float> %0, <2 x float> addrspace(1)* %out 16 ret void 17 } 18 19 ; CHECK: @fdiv_v4f32 20 ; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 21 ; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 22 ; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 23 ; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 24 ; CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS 25 ; CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS 26 ; CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS 27 ; CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS 28 29 define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { 30 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 31 %a = load <4 x float> addrspace(1) * %in 32 %b = load <4 x float> addrspace(1) * %b_ptr 33 %result = fdiv <4 x float> %a, %b 34 store <4 x float> %result, <4 x float> addrspace(1)* %out 35 ret void 36 } 37
